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	<title>Comments for Steve Leibson</title>
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	<link>http://low-powerdesign.com/sleibson</link>
	<description>Leibson's Laws and the Penalties for Breaking Them</description>
	<lastBuildDate>Wed, 18 Jan 2012 19:01:41 +0000</lastBuildDate>
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		<title>Comment on The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit by Is MRAM ramping up to the big time? &#124; Denali Memory Report</title>
		<link>http://low-powerdesign.com/sleibson/2011/09/04/the-return-of-magnetic-memory-a-review-of-the-mram-panel-at-the-flash-memory-summit/comment-page-1/#comment-3248</link>
		<dc:creator>Is MRAM ramping up to the big time? &#124; Denali Memory Report</dc:creator>
		<pubDate>Wed, 18 Jan 2012 19:01:41 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=651#comment-3248</guid>
		<description>[...] “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” [...]</description>
		<content:encoded><![CDATA[<p>[...] “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” [...]</p>
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		<title>Comment on Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W by 3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it? &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/10/25/generation-jumping-2-5d-xilinx-virtex-7-2000t-fpga-delivers-1954560-logic-cells-consumes-only-20w/comment-page-1/#comment-3247</link>
		<dc:creator>3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it? &#124; EDA360 Insider</dc:creator>
		<pubDate>Wed, 28 Dec 2011 19:14:42 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=690#comment-3247</guid>
		<description>[...] Xilinx Virtex-7 2000T FPGA using interposers with 2.5D IC assembly techniques  [...]</description>
		<content:encoded><![CDATA[<p>[...] Xilinx Virtex-7 2000T FPGA using interposers with 2.5D IC assembly techniques  [...]</p>
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		<title>Comment on Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W by 3D Thursday: Is 2.5D IC assembly “buzz-worthy”? &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/10/25/generation-jumping-2-5d-xilinx-virtex-7-2000t-fpga-delivers-1954560-logic-cells-consumes-only-20w/comment-page-1/#comment-3246</link>
		<dc:creator>3D Thursday: Is 2.5D IC assembly “buzz-worthy”? &#124; EDA360 Insider</dc:creator>
		<pubDate>Thu, 08 Dec 2011 15:14:37 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=690#comment-3246</guid>
		<description>[...] 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)” and “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”) Now Deepak Sekur, Chief Scientist at Monolithic 3D, has written his own blog titled “Is the [...]</description>
		<content:encoded><![CDATA[<p>[...] 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)” and “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”) Now Deepak Sekur, Chief Scientist at Monolithic 3D, has written his own blog titled “Is the [...]</p>
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		<title>Comment on Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W by 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/10/25/generation-jumping-2-5d-xilinx-virtex-7-2000t-fpga-delivers-1954560-logic-cells-consumes-only-20w/comment-page-1/#comment-3245</link>
		<dc:creator>3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology &#124; EDA360 Insider</dc:creator>
		<pubDate>Wed, 16 Nov 2011 18:39:37 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=690#comment-3245</guid>
		<description>[...] onto a 65nm silicon interposer. (For more information about the Xilinx Virtex-7 2000T, see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W” and “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic [...]</description>
		<content:encoded><![CDATA[<p>[...] onto a 65nm silicon interposer. (For more information about the Xilinx Virtex-7 2000T, see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W” and “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic [...]</p>
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		<title>Comment on Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers by Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/03/01/xilinx-zynq-epps-create-a-new-category-that-fits-in-among-socs-fpgas-and-microcontrollers/comment-page-1/#comment-3244</link>
		<dc:creator>Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible &#124; EDA360 Insider</dc:creator>
		<pubDate>Wed, 26 Oct 2011 14:02:04 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=502#comment-3244</guid>
		<description>[...] “Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers”    LD_AddCustomAttr(&quot;AdOpt&quot;, &quot;1&quot;); LD_AddCustomAttr(&quot;Origin&quot;, &quot;other&quot;); LD_AddCustomAttr(&quot;theme_bg&quot;, &quot;ffffff&quot;); LD_AddCustomAttr(&quot;theme_text&quot;, &quot;333333&quot;); LD_AddCustomAttr(&quot;theme_link&quot;, &quot;0066cc&quot;); LD_AddCustomAttr(&quot;theme_border&quot;, &quot;f2f7fc&quot;); LD_AddCustomAttr(&quot;theme_url&quot;, &quot;ff4b33&quot;); LD_AddCustomAttr(&quot;LangId&quot;, &quot;1&quot;); LD_AddCustomAttr(&quot;Autotag&quot;, &quot;technology&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;apps&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;arm&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;cortex-a9&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;eda360&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;fpga-prototyping&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;soc-realization&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;system-realization&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;tlm&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;virtual-prototyping-2&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;arm-cortex-a9&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;cadence&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;linux&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;multi-core-processor&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;systemc&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;xilinx&quot;); LD_AddSlot(&quot;wpcom_below_post&quot;); LD_GetBids();  Please share this now!ShareLinkedInFacebookEmailTwitterStumbleUponRedditDiggPrintLike this:LikeBe the first to like this post. [...]</description>
		<content:encoded><![CDATA[<p>[...] “Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers”    LD_AddCustomAttr(&quot;AdOpt&quot;, &quot;1&quot;); LD_AddCustomAttr(&quot;Origin&quot;, &quot;other&quot;); LD_AddCustomAttr(&quot;theme_bg&quot;, &quot;ffffff&quot;); LD_AddCustomAttr(&quot;theme_text&quot;, &quot;333333&quot;); LD_AddCustomAttr(&quot;theme_link&quot;, &quot;0066cc&quot;); LD_AddCustomAttr(&quot;theme_border&quot;, &quot;f2f7fc&quot;); LD_AddCustomAttr(&quot;theme_url&quot;, &quot;ff4b33&quot;); LD_AddCustomAttr(&quot;LangId&quot;, &quot;1&quot;); LD_AddCustomAttr(&quot;Autotag&quot;, &quot;technology&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;apps&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;arm&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;cortex-a9&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;eda360&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;fpga-prototyping&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;soc-realization&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;system-realization&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;tlm&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;virtual-prototyping-2&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;arm-cortex-a9&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;cadence&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;linux&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;multi-core-processor&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;systemc&quot;); LD_AddCustomAttr(&quot;Tag&quot;, &quot;xilinx&quot;); LD_AddSlot(&quot;wpcom_below_post&quot;); LD_GetBids();  Please share this now!ShareLinkedInFacebookEmailTwitterStumbleUponRedditDiggPrintLike this:LikeBe the first to like this post. [...]</p>
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	<item>
		<title>Comment on Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W by Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!) &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/10/25/generation-jumping-2-5d-xilinx-virtex-7-2000t-fpga-delivers-1954560-logic-cells-consumes-only-20w/comment-page-1/#comment-3243</link>
		<dc:creator>Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!) &#124; EDA360 Insider</dc:creator>
		<pubDate>Tue, 25 Oct 2011 14:09:10 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=690#comment-3243</guid>
		<description>[...] an in-depth look at the low-power design aspects of this announcement, see my blog post at [...]</description>
		<content:encoded><![CDATA[<p>[...] an in-depth look at the low-power design aspects of this announcement, see my blog post at [...]</p>
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		<title>Comment on Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory? by New memory models support system design for next year’s introduction of Everspin STT MRAMs &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2009/10/03/can-the-magneticians-finally-succeed-in-getting-mram-launched-as-a-viable-low-power-asic-nv-memory/comment-page-1/#comment-3240</link>
		<dc:creator>New memory models support system design for next year’s introduction of Everspin STT MRAMs &#124; EDA360 Insider</dc:creator>
		<pubDate>Mon, 03 Oct 2011 19:03:36 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=148#comment-3240</guid>
		<description>[...] “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?” on the www.low-powerdesign.com Web site.) Although Everspin has been shipping MRAM products for [...]</description>
		<content:encoded><![CDATA[<p>[...] “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?” on the <a href="http://www.low-powerdesign.com" rel="nofollow">http://www.low-powerdesign.com</a> Web site.) Although Everspin has been shipping MRAM products for [...]</p>
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	<item>
		<title>Comment on The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit by New memory models support system design for next year’s introduction of Everspin STT MRAMs &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/09/04/the-return-of-magnetic-memory-a-review-of-the-mram-panel-at-the-flash-memory-summit/comment-page-1/#comment-3239</link>
		<dc:creator>New memory models support system design for next year’s introduction of Everspin STT MRAMs &#124; EDA360 Insider</dc:creator>
		<pubDate>Mon, 03 Oct 2011 19:02:23 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=651#comment-3239</guid>
		<description>[...] (MRAM) including some recent coverage of a terrific MRAM panel at the Flash Memory Summit. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC [...]</description>
		<content:encoded><![CDATA[<p>[...] (MRAM) including some recent coverage of a terrific MRAM panel at the Flash Memory Summit. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC [...]</p>
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		<title>Comment on Future cars: The word from GM at IDC’s Smart Technology World conference by Is “app crashes” headline news? It is when it’s driving a car from Google &#124; EDA360 Insider</title>
		<link>http://low-powerdesign.com/sleibson/2011/05/01/future-cars-the-word-from-gm-at-idc%e2%80%99s-smart-technology-world-conference/comment-page-1/#comment-3237</link>
		<dc:creator>Is “app crashes” headline news? It is when it’s driving a car from Google &#124; EDA360 Insider</dc:creator>
		<pubDate>Mon, 08 Aug 2011 20:15:41 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=535#comment-3237</guid>
		<description>[...] spoke about such vehicles at the IDC Smart Technology Conference held in San Francisco. (See “Future cars: The word from GM at IDC’s Smart Technology World conference”) During his speech, Shaw said that to make cars that won’t crash, you need drivers that [...]</description>
		<content:encoded><![CDATA[<p>[...] spoke about such vehicles at the IDC Smart Technology Conference held in San Francisco. (See “Future cars: The word from GM at IDC’s Smart Technology World conference”) During his speech, Shaw said that to make cars that won’t crash, you need drivers that [...]</p>
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		<title>Comment on Going against the low-power grain to resurrect and improve a 31-year-old HP calculator by Geoff</title>
		<link>http://low-powerdesign.com/sleibson/2011/05/01/going-against-the-low-power-grain-to-resurrect-and-improve-a-31-year-old-hp-calculator/comment-page-1/#comment-3236</link>
		<dc:creator>Geoff</dc:creator>
		<pubDate>Thu, 07 Jul 2011 04:35:44 +0000</pubDate>
		<guid isPermaLink="false">http://low-powerdesign.com/sleibson/?p=546#comment-3236</guid>
		<description>This is the greatest HP 41 advance in 30 years.  First the 41C then Synthetics for the 41, then the 41CV, 41CX and now to top them all and to bring a calculator into the 21st century:

the HP 41CL by Monte.

Beta testing the unit now and it is fantastic!</description>
		<content:encoded><![CDATA[<p>This is the greatest HP 41 advance in 30 years.  First the 41C then Synthetics for the 41, then the 41CV, 41CX and now to top them all and to bring a calculator into the 21st century:</p>
<p>the HP 41CL by Monte.</p>
<p>Beta testing the unit now and it is fantastic!</p>
]]></content:encoded>
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