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Category Archives: SOC
Low-Power Lowdown from LSI’s Ruggero Castagnetti
“Power is a concern, a headache.” That’s how Distinguished Engineer Ruggero Castagnetti chose to start his presentation on “What’s Cool in Low Power Design” at LSI Corp’s recent 2010 Conference and Technology Showcase. However, the issue isn’t really “low power” … Continue reading
Low-Power Design with FPGAs: The Basics
Spiraling complexity in all facets of electronic design often cause us to take our eyes off the basics. A recent paper presented at the IEEE International Conference on Intelligent Control and Information Processing (ICICIP 2010), held in Dalian, China in … Continue reading
Posted in Design, FPGA, Low-Power, SOC
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SPMT engulfs LPDDR2 standard, making adoption a no-brainer. Meanwhile Marvell jumps on the bandwagon.
An insidious power problem has slowly crept up on embedded-system designers. While most of us were firmly focused on the power dissipation of our ever-expanding logic designs with their increasing number of processor cores in multicore designs, we mostly ignored … Continue reading
More on the Xilinx EPP: Three ways to communicate with on-chip peripherals
Last month I discussed the newly introduced Xilinx Extensible Processing Platform (EPP), which represents a new product line and a new venture for FPGA leader Xilinx. To briefly recap, devices in the EPP device family are essentially a high-end microcontroller … Continue reading
Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Case Studies – Part 2
In my previous blog, I discussed the hard-core features of Xilinx’s new Extensible Processing Platform (EPP) and explained the device at the 50,000-foot level. In this blog, I’ll dig a bit deeper into the thinking behind the EPP’s FPGA fabric … Continue reading
Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Part 1
Last week at the Embedded Systems Conference (ESC) held in San Jose, California, Xilinx disclosed additional information about its upcoming Extensible Processing Platform (EPP), which I previously discussed in a February 1 blog entry written just after RTECC (the Real … Continue reading
Designing Low-Power Systems with FPGAs, Part 2
Literally within an hour of posting my last blog entry on designing low-power systems with FPGAs, Altera’s marketing engine issued a related email and dropped it into my inbox. Altera’s email pre-announces the company’s upcoming FPGAs based on 28nm lithography. … Continue reading
More on Mentor’s Catapult C from John Cooley and Other Designers
Earlier this month, I wrote about Mentor’s C-to-gates synthesis tool Catapult C and low-power design. The EDA industry’s self-appointed gadfly and uber-user John Cooley has just written an extensive blog posting about Catapult C complete with detailed comments from several … Continue reading
Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x
One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading
Posted in CMOS, Design, EDA, Green Design, Low-Power, SOC
Tagged CMOS, EDA, leakage, Low-Power, process_technology, SOC
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C-to-Gates Synthesis and Low-Power Design
One of the many “pushbutton” design-automation tools that chip designers have sought is a “C-to-Gates” tool that would allow the automated development of hardware from algorithmic descriptions written in the C programming language. The place to start almost any system … Continue reading
