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Category Archives: Low-Power
Imagine no uninterruptible power supplies. I wonder if you can. A sad story of six fried hard disk drives
This is the story of six fried hard disk drives and why they died needlessly of heat failure as told to me by my good friend Ron Sartore, founder and CEO of AgigA Tech, at this month’s Flash Memory Summit. … Continue reading
Texas Instruments’ PowerStack package proves that low power is a killer app for 3D packaging
When you’re trying to eke every percentage of efficiency from a design, you leave no stone unturned. Yet an IC package is often a stone left unturned because it’s often entirely under the control of the chip vendor and besides, … Continue reading
Will Compaan’s HotSpot Parallelizer technology take us to the promised land of parallel computing?
In connection with my just-written blog entry on the massively parallel SpiNNaker project (see below), I want to relate some information about another meeting I had last March at the DATE (Design Automation and Test) conference in Grenoble, France. I … Continue reading
Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?
Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading
Cadence’s Qi Wang discusses the use of good methodology for low-power, advanced IC designs
You can read Qi Wang’s writeup of a paper on low-power IC design presented by Global Unichip’s Alex Kuo here.
Richard Goering discusses the low-power aspects of 40nm and 28nm design with Global Unichip’s Alex Kuo
Cadence blogger and long-time EDA editor Richard Goering spent some time at the recent DAC event in San Diego discussing the finer points of 40nm and 28nm design with Global Unichip’s Alex Kuo. Among the interesting tidbits from the interview … Continue reading
Need to cut IP power? (Who doesn’t?) “Press here” says Calypto
All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading
The Return of Heathkit (in spirit) at Maker Faire
I visited the most recent edition of Maker Faire last month and from what I can see, the event just keeps rolling along. I think it’s exciting to be in the company of people who love to make things. Anything. … Continue reading
The DDR4 SDRAM spec and SoC design. What do we know now?
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
Sometimes, all you need is tape: 3M Uniformity Tape solves problem of uneven LED edge lighting
We’ve all seem LCD displays with LED backlights that provide non-uniform illumination. That’s one reason why fluorescent backlights have held on for as long as they have. It’s not like anyone enjoys designing in the high-voltage power supply for the … Continue reading
