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Category Archives: Green Design
There are Direct Connections Between Low-Power Design, King Solomon’s Mines, and Kentucky Coal
I’m spending the Thanksgiving week back in my home town of Louisville, Kentucky and saw two programs on one of the PBS channels last night that reminded me of one of the reasons for driving towards low-power design with all … Continue reading
Posted in Green Design, Low-Power
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Ethernet ports, low power, and multimedia, Part 2
In the previous post, I discussed the huge potential power savings being enabled by the IEEE’s 802.1-az Ethernet specification now under development and early deployment. While IEEE 802.1-az promises to save significant amounts of power and energy through the use … Continue reading
Ethernet ports, low power, and multimedia, Part 1
When you think about the massive affects that the Ethernet standards have had on system design, the overall impact is no less than staggering—and I do not use that term lightly. Thirty years ago, when Ethernet was new, networking was … Continue reading
Posted in Design, Green Design, Low-Power, Networking
Tagged Energy Efficient Ethernet, Ethernet
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Multicore server, PC, and embedded designs push memory power, drive use of advanced DDR3 SDRAMs
Systems designers try all sorts of methods to reduce system power consumption. For years, we’ve relied on circuit tricks and have been reducing logic supply levels from the 5V power supplies that were so common in from the 1970s and … Continue reading
Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x
One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading
Posted in CMOS, Design, EDA, Green Design, Low-Power, SOC
Tagged CMOS, EDA, leakage, Low-Power, process_technology, SOC
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Green Chips in Newport Beach
Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s … Continue reading
What would you ask my panelists about Green Chip design?
I’m chairing a panel on Green Chip design at the 7th International SOC Conference next week. What would you ask the panelists about green ASIC/FPGA design if you were there? Here’s a list of panelists: “Green Chips: Technology, Trends, and … Continue reading
Posted in Design, Green Design, Low-Power
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