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Category Archives: Design
Do you believe in 21st century Intelligent Design?
Late last month, columnist Mike Cassidy wrote about visionary Clayton Christensen’s Innovator’s Dilemma in the San Jose Mercury News and his words reminded me that it was time, past time, to make yet another blog-based plea for intelligent design. No, … Continue reading
2011: A great year for low-power design, wasn’t it?
2011 was a great year for low-power design. I don’t think I can remember a year as good to low-power designers. I thought I’d devote this blog to a review of some major developments in 2011 that made low-power designers’ … Continue reading
What if 2.5D got really cheap? How would that affect low-power design?
Last week, silicon-interposer foundry Deca Technologies unstealthed. I found out from an article in the San Jose Mercury News and just published a blog about the announcement in my other blog, the EDA360 Insider. Deca is a subsidiary of Cypress … Continue reading
1972: When scientific calculators truly went low power
Dave Cochran recently wrote about his long engineering career at Hewlett-Packard on the www.hpmemory.org Web site. Who? What Web site? Well, the Web site is an amazing living museum that’s a tribute to Bill and Dave’s HP. And Dave Cochran is … Continue reading
Imagine no uninterruptible power supplies. I wonder if you can. A sad story of six fried hard disk drives
This is the story of six fried hard disk drives and why they died needlessly of heat failure as told to me by my good friend Ron Sartore, founder and CEO of AgigA Tech, at this month’s Flash Memory Summit. … Continue reading
Will Compaan’s HotSpot Parallelizer technology take us to the promised land of parallel computing?
In connection with my just-written blog entry on the massively parallel SpiNNaker project (see below), I want to relate some information about another meeting I had last March at the DATE (Design Automation and Test) conference in Grenoble, France. I … Continue reading
Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?
Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading
Need to cut IP power? (Who doesn’t?) “Press here” says Calypto
All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading
The incredible vanishing power of a machine instruction. Is this the way to the brain?
I attended DATE (Design and Test Europe) this month in Grenoble and was fascinated by Steve Furber’s keynote titled “Biologically-inspired massively-parallel architectures—computing beyond a million processors.” Furber’s introductory remarks really clarify what’s been happening to the energy cost per instruction … Continue reading
Posted in Design, Low-Power, Networking, SOC
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18th Annual Electronic Design Process Symposium brings together the top thinkers of the EDA world, April 7-8, Monterey, CA
EDPS (The Electronic Design Process Symposium) provides an exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. Attendees of this elite workshop have met each year … Continue reading
Posted in Design, EDA, Low-Power, SOC
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