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Category Archives: CMOS
What if 2.5D got really cheap? How would that affect low-power design?
Last week, silicon-interposer foundry Deca Technologies unstealthed. I found out from an article in the San Jose Mercury News and just published a blog about the announcement in my other blog, the EDA360 Insider. Deca is a subsidiary of Cypress … Continue reading
Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?
Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading
Need to cut IP power? (Who doesn’t?) “Press here” says Calypto
All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading
Tabula FPGA Scatters Logic, Memory, and Power Across Space and Time
Here’s a head-scratcher for you. Why not create tesseract FPGAs? A tesseract is the 4-dimensional version of a 3D cube. (Just as a 3D cube can be unfolded to make a set of six connected 2D squares, a tesseract can … Continue reading
Intel cuts IC power by allowing, detecting, and correcting errors
The low-power IC-design train has long ridden the rails of lowered supply voltage. However, these lowered supply rails are tangentially approaching transistor threshold voltages and have long been headed for a serious collision because transistors in large, nanometer ICs run … Continue reading
Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x
One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading
Posted in CMOS, Design, EDA, Green Design, Low-Power, SOC
Tagged CMOS, EDA, leakage, Low-Power, process_technology, SOC
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The Surprising Popularity Rise of On-Chip Memory
I attended the 7th International SOC Conference in Newport Beach last week and several of the speakers addressed issues relating to SOC and system power. One of these speakers was Bob Madge, Director of Technology Marketing at LSI Corp (formerly … Continue reading
Give OTP a chance for low-power, on-chip storage
The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so … Continue reading
Could A Low-Power Middle Ground Between ASICs/SOCs and FPGAs Help You?
You can’t always get what you want, But if you try sometime, You’ll find, You get what you need. Those lyrics from a song from the Rolling Stones describes the situation with ASICs/SOCs and FPGAs. For low power, you want … Continue reading
A Hunka, Hunka Burning CMOS (All About Latchup)
You’re a mere 10 minutes from completely understanding and preventing CMOS latchup in your low-power designs. Wizard of Oz Dave Jones has just posted his sixteenth EE Video Blog on these topics. Here it is:
