Yesterday, while walking the San Andreas fault in the Los Trancos Open Space Preserve in the Santa Cruz Mountains above Palo Alto, Paul Billig the Docent pointed out some nondescript rocks half buried along the hiking path. “These rocks don’t come from here,” he said. “They come from there,” said Paul as he pointed at a distant mountain poking through the haze about 30 miles to the south. “That’s Loma Prieta.” We know these rocks came from Loma Prieta because the chemical composition precisely matches the composition of rocks still on the mountain. Over the eons, as the Pacific plate has slipped north against the North American plate along the San Andreas fault, these rocks, which rolled off of Loma Prieta and across the fault line, have been transported north at the rate of about an inch and a half per year. That description’s similar to of one of Freescale’s two newest 32-bit microcontroller families: the Freescale ColdFire+ family that’s based on the 68000 microprocessor architecture introduced by Motorola Semiconductor in 1979. “RISCification” of the 68000 instruction set coupled with increasingly advanced process technology has dragged this processor architecture forward 30 years (rather than 30 miles) into the 21st century—and it holds up remarkably well. Together with Freescale’s new Kinetis microcontroller family based on the 32-bit ARM Cortex-M4 processor core, Freescale is striding into the current hot spot in the microcontroller war zone—the 32-bit zone. Loyalties and market shares for 8- and 16-bit microcontroller families are pretty well settled. The new front is at 32 bits and Freescale’s massive foray into this battle is a sign that there’s still territory to win.
In a world where some processor vendors are designating chips that dissipate Watts of power as “low-power” devices, Freescale’s ColdFire+ and Kinetis microcontroller families are truly low-power devices. Both families are based on 90nm process technology—for good clock speed (100-150MHz) and relatively low leakage—and feature ten similar software-selectable run, wait, and stop operating modes from full run to three successive levels of “very low leakage” stop. The ColdFire+ microcontrollers draw less than 150 microamps/MHz and the ARM Cortex-M4-based Kinetis microcontrollers draw less than 200 microamps/MHz. Their real “low-power” operation occurs when the microcontrollers enter a VLP (very low power) run mode that restricts the processor core and peripherals to a 2MHz clock, which translates into an operating current of less than 300 microamps for the two ColdFire+ microcontroller families and less than 400 microamps for the seven Kinetis families.
The ColdFire+ microcontroller introduction includes two families: Qx and Jx. Both ColdFire+ microcontroller families include several family members with different amounts of RAM, Flash EPROM, a new type of EEPROM memory called FlexMemory (for more on the innovative FlexMemory, see this blog entry from the Denali Memory Report), and a variety of peripherals. The Jx variants include USB OTG (On the Go) support. In all, there will be 40 members of this new ColdFire-based microcontroller series. The Kinetis introduction includes seven different families (K10, K20, K30, K40, K50, K60, and K70) and there will be more than 200 variants within these seven families. All seven families are upward pin-compatible and share a common set of peripheral devices making it easy to move up to more capable family members if needed.
The amount of information about these microcontrollers is massive and will take a while for you to digest, but this is a blog about low-power design so the ten operating modes deserve a bit more discussion here. The ten modes are:
- Run: Normal run mode
- VLP (Very Low Power) Run: CPU and peripheral clocks limited to 2MHz. Flash access limited to 1MHz. LVD (low-voltage detection) is off.
- Wait: Peripherals function at full speed but the processor core sleeps.
- VLP Wait: CPU is in sleep mode. Peripheral clocks limited to 2 MHz.
- Stop: Processor core in static state. Register contents maintained. LVD on.
- VLP Stop: Processor core in static state. LVD off. Some peripherals and pin interrupts operational.
- LL (low-leakage) Stop: Processor core voltage reduced to low-leakage level. Register contents retained. Exit using interrupts from various peripherals and from interrupt pins.
- VLL (very low leakage) Stop 3: Processor core voltage reduced to low-leakage level. Most internal logic powered down. All system RAM contents retained. I/O states held.
- VLL Stop 2: Like VLL Stop 3 but only some of the system RAM contents are maintained.
- VLL Stop 1: Like VLL Stop 3 but only 32 bytes of the register file are maintained.
Naturally, the deeper you go into the power-down modes, the longer it takes to wake up the microcontroller. The Kinetis microcontrollers need 4 microseconds to awake from the VLP Wait and VLP Stop modes, 35 microseconds to awake from the VLL Stop 3 and VLL Stop 2 modes, and more than 100 microseconds to awake from the VLL Stop 1 mode and to restore RAM. These ten operating modes give the embedded design team tremendous flexibility in managing system power consumption.
In addition to these 240 new 32-bit devices, Freescale has rolled out substantial development support for them in the form of an Eclipse-based CodeWarrior IDE that includes compilers for both the ColdFire+ and ARM Cortex-M4 processor cores. Freescale also provides the MQX RTOS and associated software stacks at no additional charge to ColdFire+ and Kinetis customers. There’s also a large and growing ecosystem for these parts.
