I’m chairing a panel on Green Chip design at the 7th International SOC Conference next week. What would you ask the panelists about green ASIC/FPGA design if you were there? Here’s a list of panelists:
“Green Chips: Technology, Trends, and Challenges in Low-Power Multicore SoC Designs” (http://j.mp/1D0hfW)
1. Dr. Barry Pangrle, Solutions Architect, Low Power, Design and Verification, Mentor Graphics.
2. Dr. Sho Long Chen, President, CEO, Founder and Chairman, Vweb Corporation
3. Michel Laurence co-founded Octasic.
4. Jasbinder Bhoot, Vice President, Worldwide Marketing, eASIC Corporation.
5. Jauher Zaidi, CEO, PalmChip Corporation
6. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium.
