Last week, I listened to a Webinar by Synopsys’ Jay Chiang on the DesignWare minPower IP components that the company introduced at this year’s DAC. Chiang did an excellent job and made a compelling case for using these IP components. Bottom line: some early users of DesignWare minPower IP components report as much as a 48% power savings at the block level and as much as a 24% power savings at the chip level. Those reported results should be significant enough to make every ASIC/SOC design team sit up and take notice although be cautioned, your mileage may vary (YMMV). (An archived version of the Webinar can be viewed here.)
DesignWare minPower IP components complement and do not replace existing low-power design techniques such as clock gating and the use of multi-Vt transistors. These IP components also work with more advanced low-power design approaches such as multi-voltage islands, MTCMOS (multi-threshold CMOS) logic, multi-voltage with power gating, and DVFS (dynamic voltage and frequency scaling) techniques. The minPower IP approach introduces new IP blocks at the logical design level, just after functional design and just before physicla layout. You add these new IP components by simply adding the new minPower IP database before logic synthesis.
One of the most effective ways to save power in a design is to determine the design’s functional operating modes and then to turn off whatever’s not needed in each mode. Using this approach, you can turn off the clocks to the unused blocks to cut dynamic power and you can also gate the power to these blocks, which cuts both dynamic and static power. However, you usually cannot turn off everything in a design. Something must remain awake so that the appropriate functions can be awakened at the proper time. For example, you cannot turn off the receiver in a mobile phone handset or you’ll miss incoming calls. For those blocks that cannot be shut down, you need other power-saving design approaches.
That’s where the Synopsys DesignWare minPower IP components come into play. They provide low-power logic structures that derive their low-power characteristics from one or more of three design approaches:
- Low-power datapath architectures. These datapaths are specifically designed to reduce glitches and to prevent glitches from propagating. They are also designed to minimize switching activity.
- Power- and switching-aware datapath structures. The use of these structures is based on power criteria when the synthesis tool can infer switching activity and power consumption.
- Instantiated low-power IP based on data tracking, enhanced clock gating, and data-specific datapath gating.
The DesignWare minPower datapath structures are designed to be balanced and shallow to minimize switching activity. They’re also designed to generate fewer glitches and to prevent glitch propagation. Synthesis of these datapaths also focuses on generating less switching activity by exploiting the presence of low-activity bits based on the distribution of data values moving through the pipeline. Consequently, datapath encoding is based on an analysis of operand activity through the pipeline. There’s also some amount of optimization based on variable data slack through the pipeline. Different signals propagate through a pipeline at different speeds and the DesignWare minPower IP blocks can be modified to exploit available differential slack within the pipeline to reduce power consumption.
The synthesis tool will also look for ways to reduce the number of pipeline stages that high-activity signals must propagate through and will swap the inputs on two operands entering into a function if doing so reduces power consumption. All of this evaluation would seem to require substantial amounts of simulation to evaluate the data-specific results of power optimization.
The power-aware structures in the DesignWare minPower IP collection are designed for the optimization of delay first (you still must meet timing goals), followed by power consumption and then area. Thus you might actually see some area increase with this approach if it produces substantial power savings and indeed, some of the results shown in this Webinar indicated an area increase of a few percent.
There are three IP categories within the DesignWare minPower IP line:
- Data-tracking pipelines (patented by Synopsys)
- Enhanced clock gating
- Datapath logic with built-in gating
The data-tracking pipelines are designed to suppress data bubbles within the pipeline that contain invalid data (indeterminate, glitchy data), which reduces the extraneous switching activity caused by this sort of data. These structures alone reduce power consumption on the order of 20%. That’s pretty significant. The enhanced clock gating takes the amount of clock gating in specific IP blocks from about 60% to more than 90%, which can also result in a power savings on the order of 20%. Still significant.
Even better results come from merging clock-gating logic with the datapath’s computational logic-treating the clock gating as just part of the datapath’s logic and optimizing the whole ball of wax. Power savings on the order of 30% can result.
More significant than all of the above however, is that this design approach is the Holy Grail that designers seek: a drop-in tool that requires that designers learn next to nothing while saving substantial amounts of power. Because it appears at first glance that Synopsys’ DesignWare minPower IP is just such a drop-in tool, it’s sure to get a good, close look by design teams questing for the Holy Grail of design tools.
