Ever since Intel hit the Power Wall in 2004—when the Pentium 4 drew 150W and approached 1000 pins—low-power design has come into its own. Over the past decade smart engineers have come up with a seemingly endless number of innovative tricks to stave off the frequently predicted death of Moore’s law, which was supposed to happen first at 90 nm, then 65 nm than 40 nm, etc. Still, when gate doping variations of several atoms can cause a transistor to fail, the laws of physics are finally asserting themselves. As one wit observed recently about Moore’s law, the party isn’t over but the police have arrived and the volume has been turned way down.

On one level better process technologies have gone a long way toward enabling low-power design. Smaller geometries enable lower voltage cores, which helps exponentially on the power front. Strained silicon, silicon-on-insulator, high-K metal gates and other clever process innovations have all enabled the continuing push to smaller geometries and more energy efficient designs.

On the system level design engineers have developed a long succession of power management techniques. Modern MCU’s typically rely on power gating, clock gating, and more recently dynamic (even adaptive) voltage and frequency scaling to minimize power consumption in both active and inactive modes. With the number of sleep modes and voltage islands proliferating, fine-grained power management becomes so complex that most CPUs now rely on separate power management ICs (PMICs). Since MCU’s are more self-contained, much of the power management burden is shifted from the embedded developer back to the chip designer.

Low Power –> Ultra-Low Power

If not the chips then the ‘race to the bottom’—in terms of power—between MCU vendors is getting heated. With the numbers they’re hitting, it’s hard to argue that the newest MCUs are indeed ‘ultra-low power’.

TI promotes its 16-bit RISC ‘ultra-low power’ MSP430 line in a wide range of applications, including a wireless sensor circuit that can operate from a single coin cell for up to five years (thanks in part to a very short duty cycle). The MSP430C1101—with 1kB of ROM, 128B RAM, and an analog comparator—draws 160 µA at 1 MHz/2.2V in active mode, 0.7 µA in standby mode, and 0.1 µA in off mode. This week TI announced its Grace software platform, a free plug-in for Code Composer Studio that provides a detailed graphical user interface to simplify low-level programming of MSP430 MCUs.

Microchip’s answer to the MSP430 is its eXtreme Low Power PIC Microcontrollers with XLP Technology.  XLP processors include 16 to 40 MIPS PIC24 MCU & dsPIC DSC families with up to 256 KM of memory and a variety of I/O options. On its web site Microchip emphasizes how low power its devices are in deep sleep mode, comparing the PIC24F16KA102 favorably to the MSP430F2252 LPM3 at 3V. Comparing power in active modes is considerably more complex, being highly application dependent. That’s what evaluation kits are for.

Silicon Labs claims that its C8051F9xx ultra-low-power product family includes “the most power-efficient MCUs in the industry,” with both the lowest active and sleep mode power consumption (160 µA/MHz /50 nA for the C8051F90x-91x) compared to “competitive devices.” Comparing data sheets is often and exercise in “apples and oranges,” but the numbers do justify the impression that ‘ultra-low power’ is a lot more than marketing hype.

NXP is definitely into green MCUs with its GreenChip ICs that “improve energy efficiency and reduce carbon emissions.” NXP’s recently announced LPC11U00—being a Cortex-M0-based MCU—is decidedly low power, but this one focuses more on connectivity, incorporating a USB 2.0 controller, two synchronous serial port (SSP) interfaces, I²C, a USART, smart card interface3 and up to 40 GPIO pins.

STMicroelectronics features 8- and 32-bit families of ultra-low-power MCUs, apparently skipping over the 16-bit migration path that Microchip needed to fill. The 8-bit STM8L15xx CISC devices can run up to 16 MIPS at 16 MHz but still only draw 200 µA/MHz in active mode and 5.9 µA down to 400 nA in various sleep modes. Like NXP, ST is into connectivity, including a wide range of options on different devices.

Connectivity and flexibility are the main selling point for Cypress’ programmable system-on-chip or PSoC. PSoC 5 is based on a 32-bit Cortex-M3 core running up to 80 MHz. Incorporating a programmable, PLD-based logic fabric, the CY8C54 PSoC family can handle dozens of different data acquisition channels and analog inputs on every GPIO pin. The chip draws 2 mA in active mode at 6 MHz, 2 µA in sleep mode (with RTC) and 330 nA in hibernate with RAM retention.

Grill the Gurus

If after reading all the datasheets you still have questions, this Thursday you can ‘grill the gurus’ online in real time as EE times presents the Digi-Key Microcontroller Virtual Conference: New Directions in MCU Designs, from 11-6 EDT. From 11:15-12:15 EDT I’ll be moderating the panel “Low-Power Design—Keeping Hot Designs Cool,” and questions from the audience are encouraged.

From 12:30-1:30 EDT Scott Roller, Vice President and General Manager, Microcontrollers at Texas Instruments will deliver the keynote, “What Will Make The Biggest Impact: Low Power? Connectivity? Simplicity? Yes.” TI sees the market for embedded MCUs exploding over the next several years, and it’s working on some interesting innovations that should open up new markets for developers.

Throughout the day there will be series of panels, webcasts, chats and exhibits at (virtual) pavilions of interest to the embedded design community. Click here to check it out. I hope to see you there.

USB has become the most successful PC peripheral interconnect ever defined, with over 10 billion USB 2.0 products installed today. Still, despite its convenience, USB has never been either the fastest or the lowest-power interconnect protocol out there. USB 3.0 seriously attempts to address both of those problems.

Facing competition from other high-speed interconnect protocols like 400- and 800-Mbps IEEE-1394 (FireWire) and HDMI—both of which targeted high-data rate streaming of video—in 2008 the USB Implementers Forum (USB-IF) formalized the specification for USB 3.0, which promises a “SuperSpeed” data rate of 5Gb/sec, a 10x improvement over USB 2.0 while at the same time reducing power consumption.

How can they do that you ask?

For starters, by eliminating polling. A USB 2.0 host continuously polls all peripheral devices to see if they have data to send to the host controller. All devices must therefore be on at all times, which not only wastes power but adds unnecessary traffic to the bus. In USB 3.0 polling is replaced by asynchronous notification. The host waits until an application tells it that there is a peripheral with data it needs to send to the host. The host then contacts that peripheral and requests that it send the data. When both are ready, the data is transferred.

USB 2.0 is inherently a broadcast protocol. USB 3.0 uses directed data transfer to and from the host and only the target peripheral. Only that peripheral turns on its transceiver, while others on the bus remain in powered-down mode. This results in less bus traffic and a considerably lower power profile.

SuperSpeed USB enables considerable power savings by enabling both upstream and downstream ports to initiate lower power states on the link. In addition multiple link power states are defined, enabling local power management control and therefore improved power usage efficiency. Eliminating polling and broadcasting also went a long way toward reducing power requirements. Finally, the increased speed and efficiency of USB 3.0 bus – combined with the ability to use data streaming for bulk transfers – further reduces the power profile of these devices. Typically the faster a data transfer completes, the faster system components can return to a low-power state. The USB-IF estimates the system power necessary to complete a 20 MB SuperSpeed data transfer will be 25% lower than is possible using USB 2.0.

The SuperSpeed specification brings over Link Power Management (LPM) from USB 2.0. LPM was first introduced in the Enhanced Host Controller Interface (EHCI) to accommodate high-speed PCI-based USB interfaces. Because of the difficulty of implementing it, LPM was slow to appear in USB 2.0 devices. It’s now required in USB 3.0 and for SuperSpeed devices supporting legacy high-speed peripherals. LPM is an adaptive power management model that uses link-state awareness to reduce power usage.

LPM defines a fast host transition from an enabled state to L1 Sleep (~10 µs) or L2 Suspend (after 3 ms of inactivity). Return from L1 sleep varies from ~70 µs to 1 ms; return from L2 Suspend mode is OS dependent. The fast transitions and close control of power at the link level enables LPM to manage power consumption in SuperSpeed systems with greater precision than was previously possible.

Link Power Management

Link power management enables a link to be placed into a lower power state when the link partners are idle. The longer a pair of link partners remain idle, the deeper the power savings that can be achieved by progressing from UO (link active) to Ul (link standby with fast exit), to U2 (link standby with slower exit), and finally to U3 (suspend). The table below summarizes the logical link states.

Most SuperSpeed devices, sensing inactivity on the link, will automatically reduce power to the PHY and transition from U0 to U1. Further inactivity will cause these devices to progressively lower power. The host or devices may then further idle the link (U2), or the host may even suspend it (U3).

Both devices and downstream ports can initiate Ul and U2 entry. Downstream ports have inactivity timers used to initiate Ul and U2 entry. Downstream port inactivity timeouts are programmed by system software. Devices may have additional information available that they can use to decide to initiate Ul or U2 entry more aggressively than inactivity timers. Devices can save significant power by initiating Ul or U2 more aggressively rather than waiting for downstream port inactivity timeouts.

Backward Compatibility

While the advantages of SuperSpeed USB are impressive, these devices are just beginning to appear in a world dominated by USB 2.0. For backward compatibility SuperSpeed devices must support both USB 2.0 and 3.0 link speeds, maintaining separate controllers and PHYs for full-speed, high-speed and SuperSpeed links. By maintaining a parallel system to support legacy devices, SuperSpeed’s designers accepted higher cost and complexity as a price worth paying to avoid compromising the speed advantage of their new architecture.

Just as they have for the last several years, portable devices will continue to drive growth in the electronics industry. Far from just handsets, the mobile internet—also encompassing “the internet of things”—represents a huge expansion of the semiconductor application space to include a wide range of wireless home entertainment, automotive safety and autonomous industrial, military and medical devices. The mobile internet promises to be 10-100x larger in unit volume than the desktop internet ever was.

Amerasekera distinguishes between two types of portable electronics: performance “hub” devices such as computers, multi-media devices, wireless hubs and PDAs which have 1W to 5W needs today; and distributed, largely autonomous systems with micro and nano watt needs. A typical autonomous system—for example, wireless strain gauges in bridges and aircraft wings—has a life expectancy of up to 10 years. Assuming such a device is powered by today’s typical 100 mAh cell phone battery, the average power available from the battery is less than 1 µW. That isn’t possible with today’s technologies.

The problem is that battery technology has been scaling at about 2x every 10 years compared to semiconductor technology, which scales 2x every 18 months. The gap between what portable electronic devices demand and what batteries can deliver will continue to grow. Don’t expect much improvement from the battery camp any time soon. “The energy density of lithium-ion batteries is so high that they’re really like small hand grenades,” said Amerasekera. There isn’t much left on the atomic scale that has a higher energy density and isn’t radioactive.

How Do You Manage?

Lacking more capable batteries, silicon performance advances require power management. A lot of very effective techniques have been developed over the last several years. At 65 nm leakage power was reduced 300x vs. what it had been at 90 nm through a combination of SDRAM retention, logic power gating, channel length reduction, logic retention, process/temperature AVS and dynamic voltage and frequency scaling (DVFS). At 45 nm new techniques were devised—including adaptive body bias (ABB) and Retention ‘Til Access (RTA)—that resulted in 1000x reduction in active power. Still, Amerasekera—like Jan Rabaey in his keynote yesterday—is concerned that we’ve run out of tricks at the component level that will scale.

According to Amerasekera, future advances in ultra-low-power electronics will come at the system level. He gives the example of running an FFT in software, which requires 28 uW. Running it in hardware requires only 1.6 uW, an 18x improvement. Dropping the core voltage yields a further 1.8x power savings, for a total improvement of 28x. The SoC running the FFT now draws < 1uA.

3D chip techniques have finally evolved to the point where they can help optimize bandwidth, power and area. Currently 3D means package on package (POP) or stacked die. FinFET technology now enables more dense dies, and and die-to-die interconnects—vias connecting disparate digital, analog and RF layers—are becoming…viable.

Renewable energy—wind, solar, hydro and heating systems—has tremendous potential, though they’re all faced with economic as well as technical challenges. Energy harvesting also has a lot of potential, but efficiencies of such systems are quite low, as is the amount of energy they can deliver. Still, there’s a place for them going forward.

Divide and Conquer

Basically, the mobile internet will need a variety of energy sources:

• Batteries for general functionality
• Storage caps for high current functions
• Energy scavenging for extended battery life
• Wireless power sources for connection to the grid

The mobile internet will also require intelligent energy management and control, including

• Highly efficient on-chip power processing
• Control of energy sources and delivery
• Management of power demand and access
• Unreliable energy sources (aka wind, solar, etc.)

The challenge for the next decade will be coming up with another 2-3 orders of magnitude of power reduction to meet the demands of an increasingly wireless world.

Engineers always enjoy working on interesting problems, and this one should stay interesting for years to come.