Last month in Santa Rosa, CA, an electric-powered 4-seat light plane won the NASA/Google Green Flight Challenge by flying over 200 miles non-stop at over 100 MPH while achieving 403.5 passenger miles per gallon (mpg) using the equivalent of less than one gallon of gasoline. Compare that to the Chevy Volt—the current state of the art in electric (land-based) vehicles—which gets the equivalent of 112 mpg in all-electric mode while driving slowly over flat roads. And even with the benefit of wheels and a 435 lb. battery, the Volt can only keep that up for 35 miles, at which point it reverts to its gas engine, which gets 37 mpg.

The winner of the $1.65 million prize was Team Pipistrel from Penn State, flying a Taurus G4 manufactured in Slovenia. The G4 is a four-seat, twin engine plane with a wingspan of 69’2” and weighing 2,490 lb, slightly less than a Volkswagen Beetle. The two 145 KW (194 HP) motors can drive Pipistrel to about 114 mph, so it won the Challenge race running almost flat out.

Detailed data on the custom-built G4 is hard to come by, but not for the production model Taurus Electro G2. The body is a composite of epoxy resin, fiberglass, carbon fibers and Kevlar in a honeycomb structure. The motor is a high-performance synchronous 3-phase outrunner with permanent magnets, delivering 40 kW on takeoff and 30 kW continuous. The best glide ratio is 1:41, which really qualifies it as a powered glider. To put it in perspective, the typical glide ratio for a two-seat general aviation plane is about 1:10. Aside from getting unimpressive mileage, you really don’t want to run out of gas while flying your Piper Cub. Or in a 747 for that matter.

Electric gliders have been around for a while. The first commercial one was the AE-1 Silent, which first flew in 1997. Weighing a mere 430 lb., the AE-1 is easily powered by its 13 kW (17 Hp) electric motor, which in turn works from a 4.1 kW/77 lb. Li-Ion battery. If you’re so inclined the AE-1 is FAA certified as an ultralight aircraft and it’s still being produced.

More high powered is the Antares 20E from Lange Aviation GmbH, in production since 2004. The 20E is powered by a 42 kW (52 hp) BLDC electric motor weighing 64 lb. Energy storage consists of 72 Li-Ion cells each rated at 44 Ah at 3.7V, for a combined capacity of 12 kWh @ 266V. With a wingspan of 65 ft. and weighing in at 1,455 lb, this is a serious airplane—though still a one seater. The 20E can self launch and climb to 3,300 ft. in four minutes and climb to 10,000 ft., where it can fly for 1.5 hours. Assuming you’ve covered 93 miles at that point and a maximum glide ratio of 1:56 (!), the maximum range then becomes (93+(2×56))=205 miles.

Now let’s figure the mileage for just the powered portion of the flight. Assuming your flight fully depleted the 12 kWh batteries, that works out to 12 kWh/93 miles or 12.9 kWh/100 miles. Using the same formula the EPA applied to the Chevy Volt—where 36 kWh/100 miles = 93 mpg-e—the Antares comes in 2.8x better at 260 mpg equivalent! That’s a pretty energy efficient way to travel.

In an interesting twist Lange is now producing the Antares DLR-H2, which is powered by hydrogen fuel cells, with the tanks slung in pods under the wings. The actual motive force is a 42 kW BLDC motor. The 130 lb. fuel cells can generate 20 kW continuously, twice the 10 kW required for level flight. The DLR-H2 can attain a height of 12,000 ft and has a top speed of 105 mph and a range of 1,240 miles.

Using solar cells to recharge your batteries while in flight can greatly extend your range. In 1990 the solar powered plane Sunseeker flew across the U.S. powered by a 250W array of thin-film solar cells. Since solar cells obviously don’t work at night, it took two weeks to accomplish this task.

The first solar powered plane to complete a 24 hour flight was Solar Impulse. Claiming to have “the wingspan of an Airbus [208 ft.]…the weight of a family car [3,500 lb.]…and the power of a scooter [40 hp],” its designers plan to fly it around the world in 2012. The solar cells on the wings of Solar Impulse cover 650 sq. ft. and can generate 6 kW (8.2 hp), which is stored in Li-Ion cells during the night. All things being equal, this should be enough to keep the 1.6 ton plane aloft day and night while traveling at just over 40 mph.

Even electric commercial airliners are in the works. In Europe EADS, Airbus’ parent company, has proposed the VoltAir ducted fan engine that would power commercial airliners. To achieve the energy density required to move such a massive aircraft, the VoltAir motor would be constructed of high-temperature superconducting (HTS) materials, cooled by liquid nitrogen. HTS motors are expected to reach power densities of 7-8 kW/kg, comparable to 7 kW/kg for today’s turboshaft engines. The batteries will still be Li-Ion, which EADS hopes will become more efficient, or Li-Air should it become commercially viable by then.

Coming to an Airport Near You

While electric flight is both fun and interesting—especially to engineers—it may impact you sooner than you think. Every major city and most smaller ones have general aviation airports. The Taurus G2 and numerous others like it would make quiet, inexpensive air taxis practical. Not only are the planes inexpensive—about the cost of a high-end car—they’re extremely inexpensive to operate, highly reliable, quiet, and essentially non-polluting. Instead of fighting the traffic between New York and Boston or San Jose and Sacramento you would be able to hop a quick, cheap flight there and gaze smugly down at the congestion below.

So there you have it. Electric boats and cars—been there, done that. Stay tuned for electric aircraft. You hopefully won’t have to stay tuned for long, and it will be worth the wait.

USB has become the most successful PC peripheral interconnect ever defined, with over 10 billion USB 2.0 products installed today. Still, despite its convenience, USB has never been either the fastest or the lowest-power interconnect protocol out there. USB 3.0 seriously attempts to address both of those problems.

Facing competition from other high-speed interconnect protocols like 400- and 800-Mbps IEEE-1394 (FireWire) and HDMI—both of which targeted high-data rate streaming of video—in 2008 the USB Implementers Forum (USB-IF) formalized the specification for USB 3.0, which promises a “SuperSpeed” data rate of 5Gb/sec, a 10x improvement over USB 2.0 while at the same time reducing power consumption.

How can they do that you ask?

For starters, by eliminating polling. A USB 2.0 host continuously polls all peripheral devices to see if they have data to send to the host controller. All devices must therefore be on at all times, which not only wastes power but adds unnecessary traffic to the bus. In USB 3.0 polling is replaced by asynchronous notification. The host waits until an application tells it that there is a peripheral with data it needs to send to the host. The host then contacts that peripheral and requests that it send the data. When both are ready, the data is transferred.

USB 2.0 is inherently a broadcast protocol. USB 3.0 uses directed data transfer to and from the host and only the target peripheral. Only that peripheral turns on its transceiver, while others on the bus remain in powered-down mode. This results in less bus traffic and a considerably lower power profile.

SuperSpeed USB enables considerable power savings by enabling both upstream and downstream ports to initiate lower power states on the link. In addition multiple link power states are defined, enabling local power management control and therefore improved power usage efficiency. Eliminating polling and broadcasting also went a long way toward reducing power requirements. Finally, the increased speed and efficiency of USB 3.0 bus – combined with the ability to use data streaming for bulk transfers – further reduces the power profile of these devices. Typically the faster a data transfer completes, the faster system components can return to a low-power state. The USB-IF estimates the system power necessary to complete a 20 MB SuperSpeed data transfer will be 25% lower than is possible using USB 2.0.

The SuperSpeed specification brings over Link Power Management (LPM) from USB 2.0. LPM was first introduced in the Enhanced Host Controller Interface (EHCI) to accommodate high-speed PCI-based USB interfaces. Because of the difficulty of implementing it, LPM was slow to appear in USB 2.0 devices. It’s now required in USB 3.0 and for SuperSpeed devices supporting legacy high-speed peripherals. LPM is an adaptive power management model that uses link-state awareness to reduce power usage.

LPM defines a fast host transition from an enabled state to L1 Sleep (~10 µs) or L2 Suspend (after 3 ms of inactivity). Return from L1 sleep varies from ~70 µs to 1 ms; return from L2 Suspend mode is OS dependent. The fast transitions and close control of power at the link level enables LPM to manage power consumption in SuperSpeed systems with greater precision than was previously possible.

Link Power Management

Link power management enables a link to be placed into a lower power state when the link partners are idle. The longer a pair of link partners remain idle, the deeper the power savings that can be achieved by progressing from UO (link active) to Ul (link standby with fast exit), to U2 (link standby with slower exit), and finally to U3 (suspend). The table below summarizes the logical link states.

Most SuperSpeed devices, sensing inactivity on the link, will automatically reduce power to the PHY and transition from U0 to U1. Further inactivity will cause these devices to progressively lower power. The host or devices may then further idle the link (U2), or the host may even suspend it (U3).

Both devices and downstream ports can initiate Ul and U2 entry. Downstream ports have inactivity timers used to initiate Ul and U2 entry. Downstream port inactivity timeouts are programmed by system software. Devices may have additional information available that they can use to decide to initiate Ul or U2 entry more aggressively than inactivity timers. Devices can save significant power by initiating Ul or U2 more aggressively rather than waiting for downstream port inactivity timeouts.

Backward Compatibility

While the advantages of SuperSpeed USB are impressive, these devices are just beginning to appear in a world dominated by USB 2.0. For backward compatibility SuperSpeed devices must support both USB 2.0 and 3.0 link speeds, maintaining separate controllers and PHYs for full-speed, high-speed and SuperSpeed links. By maintaining a parallel system to support legacy devices, SuperSpeed’s designers accepted higher cost and complexity as a price worth paying to avoid compromising the speed advantage of their new architecture.

The basic structure of the electric grid today is not much different than it was 100 years ago, other than the fact that it supplies AC rather than DC. Reasons for modernizing the grid include reducing costs; using more renewables; improving reliability; and supporting electric vehicle recharging.

The arguments on the cost side are compelling. Half of all U.S. coal plants are over 40 years old, and the cost of upgrading or replacing them is estimated at $560 billion by the year 2030. Smart Grid technology can reduce both peak and average electrical usage, reducing the required investment. There’s also considerable leeway for conservation. In the United States per capita annual electricity usage is 13,000 kWh. In Japan the per capita usage is 7900 kWh. By providing feedback to consumers on their usage patterns and enabling them to shift loads to nonpeak – and therefore lower cost – hours, smart grids provide the feedback loop to consumers both enabling and incentivizing them to conserve electricity.

The US has nowhere to go but up in the use of renewable energy sources. The vast majority of our electricity comes from coal-fired power plants. According to the Department of Energy renewables account for only 8.4% of US electrical generation, with Hydro contributing 5.95%, wind only 0.83% and solar even less.

On the reliability issue: the average U.S. utility customer experiences 125 min. of power outages per year; the average Japanese consumer only has to put up with that for 16 min. per year. The estimated cost of these power outages to the US economy according to the department energy is approximately $80 billion per year.

Turning to the demand side, where does the power go? Residential use accounts for 37%, commercial usage is 36% and industrial applications account for the remaining 27%. On the residential side 17% of your electricity goes to air conditioning, 15% to lights, 9% to heating and the balance to other devices. Getting your kids to turn off the lights will help, but only so much.

Arnold spent some time discussing smart appliances. Smart appliances will need home control systems in order to store your preferences for them; it won’t be up to the electric utility to determine when and which appliances you run. This event was heavily supported by numerous players in the smart appliance and home control markets, including the HomePlug Powerline Alliance, the HomeGrid Forum, the Z-Wave Alliance, the Wi-Fi Alliance and numerous semiconductor, system and utility providers. The stakeholders came to share ideas and hear what NIST had to say.

As well they might. As Arnold asked rhetorically, “With a dozen different communications interfaces, how do you do a national Smart Grid?” Good question. Right now just about every RF protocol you’ve heard of – and some you may not have – is vying to be part of the smart grid. Lacking any kind of standardization, and with plenty of money invested in proprietary solutions, utilities are understandably reluctant to move forward with Smart Grid implementations, and consumers are at least as confused.

NIST has now finished reviewing the various protocols and is now passing that information back to industry to work out standards. In Arnold’s words, “Things are about to become very contentious and argumentative” as standards are hashed out. As Bismarck once remarked, “If you like laws and sausages, you should never watch either one being made.” The same certainly applies to electronics standards.

There actually is real progress being made, and we’ll report on that shortly. Meanwhile don’t despair, the Smart Grid really is happening. It’s just not going to be happening next week.

Just as they have for the last several years, portable devices will continue to drive growth in the electronics industry. Far from just handsets, the mobile internet—also encompassing “the internet of things”—represents a huge expansion of the semiconductor application space to include a wide range of wireless home entertainment, automotive safety and autonomous industrial, military and medical devices. The mobile internet promises to be 10-100x larger in unit volume than the desktop internet ever was.

Amerasekera distinguishes between two types of portable electronics: performance “hub” devices such as computers, multi-media devices, wireless hubs and PDAs which have 1W to 5W needs today; and distributed, largely autonomous systems with micro and nano watt needs. A typical autonomous system—for example, wireless strain gauges in bridges and aircraft wings—has a life expectancy of up to 10 years. Assuming such a device is powered by today’s typical 100 mAh cell phone battery, the average power available from the battery is less than 1 µW. That isn’t possible with today’s technologies.

The problem is that battery technology has been scaling at about 2x every 10 years compared to semiconductor technology, which scales 2x every 18 months. The gap between what portable electronic devices demand and what batteries can deliver will continue to grow. Don’t expect much improvement from the battery camp any time soon. “The energy density of lithium-ion batteries is so high that they’re really like small hand grenades,” said Amerasekera. There isn’t much left on the atomic scale that has a higher energy density and isn’t radioactive.

How Do You Manage?

Lacking more capable batteries, silicon performance advances require power management. A lot of very effective techniques have been developed over the last several years. At 65 nm leakage power was reduced 300x vs. what it had been at 90 nm through a combination of SDRAM retention, logic power gating, channel length reduction, logic retention, process/temperature AVS and dynamic voltage and frequency scaling (DVFS). At 45 nm new techniques were devised—including adaptive body bias (ABB) and Retention ‘Til Access (RTA)—that resulted in 1000x reduction in active power. Still, Amerasekera—like Jan Rabaey in his keynote yesterday—is concerned that we’ve run out of tricks at the component level that will scale.

According to Amerasekera, future advances in ultra-low-power electronics will come at the system level. He gives the example of running an FFT in software, which requires 28 uW. Running it in hardware requires only 1.6 uW, an 18x improvement. Dropping the core voltage yields a further 1.8x power savings, for a total improvement of 28x. The SoC running the FFT now draws < 1uA.

3D chip techniques have finally evolved to the point where they can help optimize bandwidth, power and area. Currently 3D means package on package (POP) or stacked die. FinFET technology now enables more dense dies, and and die-to-die interconnects—vias connecting disparate digital, analog and RF layers—are becoming…viable.

Renewable energy—wind, solar, hydro and heating systems—has tremendous potential, though they’re all faced with economic as well as technical challenges. Energy harvesting also has a lot of potential, but efficiencies of such systems are quite low, as is the amount of energy they can deliver. Still, there’s a place for them going forward.

Divide and Conquer

Basically, the mobile internet will need a variety of energy sources:

• Batteries for general functionality
• Storage caps for high current functions
• Energy scavenging for extended battery life
• Wireless power sources for connection to the grid

The mobile internet will also require intelligent energy management and control, including

• Highly efficient on-chip power processing
• Control of energy sources and delivery
• Management of power demand and access
• Unreliable energy sources (aka wind, solar, etc.)

The challenge for the next decade will be coming up with another 2-3 orders of magnitude of power reduction to meet the demands of an increasingly wireless world.

Engineers always enjoy working on interesting problems, and this one should stay interesting for years to come.

U.C. Berkeley professor Jan Rabaey kicked off the 2010 International Symposium on Low-Power Electronics and Design (ISLPED) today in Austin with a challenge to programmers, hardware designers and their EDA tool providers: The deterministic Turing model has hit the power wall. If you want energy efficiency, forget accuracy. Consider statistical, even analog computing.

In his keynote talk—“Going Beyond Turing: Energy Efficiency in the Post-Moore Era”—Rabaey claimed that despite a decade of advances in energy efficiency—including dynamic and adaptive voltage scaling, architectural innovations and other clever power management techniques—“waste has been eliminated and we’re basically running out of options” at smaller geometries. In fact at 22 nm and below, energy savings won’t scale any more. Leakage is now the major problem, and scaling makes it worse. ISSCC 2011 will feature a general session panel that will brainstorm how to get the next major power reduction as you scale down.

It’s Hard to Determine

All computers today are built on a deterministic model; with the same inputs you get the same outputs every time. But what if you don’t need complete accuracy—if “being in the ballpark” is good enough? According to Rabaey, “If you’re willing to back away a bit from accuracy, you can gain quite a bit in efficiency.” You can get along with a lot less computing power if you’re willing to accept a range of outputs.

Why not in fact do the computation in analog? The outcome will be not a single number but a distribution. Analog is inherently accurate for simple computations, but improving accuracy is expensive in terms of energy efficiency, since in analog circuits there is an exponential relationship between the signal-to-noise ratio (SNR) and power. For up to a 30 dB SNR, analog does a good job; but to get better SNR, the power requirement goes up fast. There are a lot of applications that do well with a low SNR. While not exactly an application, the basically analog human brain works very well at a low SNR. Add a room full of screaming 7-year olds and its efficiency falls off a cliff.

Statistical computing doesn’t rely on probabilistic algorithms and it’s not the same as Boolean networks. Its inputs are deterministic or stochastic variables and its outputs are a range of numbers that follow a distribution curve. It relies on algorithms that display resilience in the presence of uncertainty (“noise”) and can still make reasonable estimates—with varying degrees of certainty—within parameters determined by the degree of uncertainty associated with the inputs.

ERSA and ANTs

Rabaey cited work done at Stanford on the Error Resistant System Architecture (ERSA), an attempt to define a hardware/software architecture that supports statistical computing. ERSA has resulted in significant power savings in dealing with streaming video, adding little detectable noise in the process. Rabaey also cited experiments on algorithmic noise tolerance (ANT) that resulted in a 2.5x energy saving for a barely detectable increase in error rate.

Rabaey pointed out that some applications are well suited to statistical computing techniques while others are not. Adding a bit of noise to streaming video is a reasonable tradeoff if it results in a major power saving. In contrast, medical, military and any mission-critical computing tasks need to remain deterministic. “Some errors roll off smoothly, while some are catastrophic.” And in any application, changes to the least significant bit (LSB) in a byte may be insignificant, while changes to the most significant bit (MSB) clearly are not.

Statistical computing may hold great promise, but designers and programmers need to change their thinking and EDA vendors need to deliver the tools. “We must start building statistics into all levels of the design process,” Rabaey concluded. “We have to break determinism. VHDL and Verilog are purely deterministic languages. We must spend time on error modeling of our hardware.” For this to happen, “The EDA community really needs to break out into the application space.”

Mentor, Synopsys, Cadence: the ball’s in your court, folks.

By any measure the conference was a success: 1,304 people attended, with 555 attending the Low-Power Design panel and 447 catching the Software, Tools & Operating Systems panel. This is certainly testimony to the quality of the speakers but more broadly to the breadth of the ARM designer community and their eagerness to hear and share insights that will help with their next ARM-based design. In that regard they weren’t disappointed.

Over a period of several hours the panels, webinars, chats and vendor pavilions delivered, frankly, more information than I could absorb—and all without any of us getting sore feet. [Full disclosure: I did miss the free beer at 5 o’clock.]

The Low-Power Design panelists—from Cadence, Synopsys, National Semiconductor and TI—all agreed with ARM’s CTO Mike Muller’s assertion in his keynote that silicon-on-insulator (SoI) looks very promising, especially now that an ecosystem is forming and the process price is falling. The panelists from Cadence and Synopsys concurred that the differences between CPF and UPF are by now fairly trivial, the remaining challenge being to integrate power awareness farther up the toolchain past RTL. National and TI detailed their different approaches to power management, though both agreed that power-aware software—from the application to the compiler level—are where system designers now need to focus their attention. Synopsys has indicated that they’re taking that tack with their recent acquisition of CoWare, who have long been focused on system-level design.

The New Frontiers for ARM Cores panelists—from ARM, NXP, Cypress and the SoI Consortium—discussed ARM’s forays into both the low-end, 8-bit MCU market and high-end, high-speed 32-bit applications. ARM claims that its 32-bit Thumb-2 compiled code is both smaller and faster than that for 8-bit microcontrollers, most of which are 20-year-old designs; and that working at smaller geometries provides a cost advantage over older processes. On the high end the panelists all expect to see multicore become almost ubiquitous, though the silicon is moving faster than the tools required to program it. They also agreed that programmable hardware has a role to play going forward, whether that includes dropping processors and peripherals into an FPGA for low- to mid-volume production or including a programmable fabric in an SOC.

The Software, Tools and Operating Systems panelists—from ExpressLogic, Mentor Graphics, CoWare, and Green Hills Software—took direct aim at the software part of the design equation. The participants—admittedly all RTOS vendors—insisted that all but the smallest 8-bit applications require an operating system, which relieves the developer of low-level coding, thereby reducing complexity, not adding to it. The panelists took some heat about needing better tools—on which they are diligently working—but they also pointed out that some of the “software problem” is self-inflicted, since designers often don’t consider test and debug until they are too far into the design process. The number of corner cases you need to test and verify in today’s highly complex embedded systems has grown geometrically in recent years, placing a considerable burden on both designers and their tool vendors.

In a separate webinar titled Cracking the Multi-layer Design Code, Sonics detailed how to cost-effectively simplify and optimize an AMBA-based design. Sonics takes an on-chip network approach to solving the knotty problem of communicating between multiple cores in a complex SoC. If your design is still based on the AHB bus, migrating from a multi-layer to a concurrent AHB design can address the routability and scaling issues inherent in the older approach. Sonics also detailed the conversion steps to take if you’re moving up to an AMBA-based design.

Three scheduled chats provided some lively feedback, not to mention entertainment:

• Is ARM’s Cortex-A8 an Atom Smasher? dived right into the collision between ARM and Intel in the netbook space and beyond. ARM is the likely winner, but it won’t happen overnight.

• Why is One ARM Different from Any Other? sought to sort out the large number of permutations of ARM products and their intended applications. Even developers have trouble keeping up.

• Get Ready for SoI highlighted the limitations of bulk CMOS at smaller line widths and the power-saving advantages of SoI. The SoI Consortium is assembling an ecosystem of fabs, hardware and tool vendors to help move SoI into the mainstream.

Finally the vendor booths on the (virtual) pavilion floor provided an opportunity to chat with vendor reps and ask their FAEs to help solve your design problems. I did my usual routine and grabbed all the brochures and white papers in sight, only this time I didn’t have to FedEx them back to my office.

I’d briefly attended one of these virtual conferences before, but this is the first time I’ve been actively involved as a co-chair. Being on a virtual panel felt exactly like being on a live one, I just couldn’t see the panelists’ faces. The volume of information was as high as at any live trade show, but the decibel level was considerably more comfortable. While I still miss the “free beer at 5:00,” from the attendee’s standpoint I think these things are a low-impact (on your time), high-value proposition that nicely supplements—though won’t replace—live trade shows. If you haven’t attended a virtual conference, I recommend you check one out.

These little boxes are ubiquitous and inconspicuous but hardly innocuous. I’ve got 14 of them in my house alone. As of 2005 they reportedly consumed four percent of the electricity used by the average U.S. home, or over one percent of total U.S. power consumption.

Wall warts to date have been simple linear supplies with transformers that suck electricity 24/7 whether anything is connected to them or not. Typically 50-80% of the power they consumed was lost as heat.

In 2002 the Natural Resources Defense Council started talking to manufacturers, utilities and the government about shifting to solid-state converters. Two years later the EPA mandated increased energy efficiency in wall warts, which is resulting in a wholesale conversion from transformer-based to IC-based devices with 80-90% efficiency. As the Economist points out,

“For consumers the switch has meant lower power bills and smaller, lighter power adaptors. For the world as a whole it has meant a sharp drop in global power consumption worth around $2 billion a year—saving 13m tons of CO₂ annually worldwide, the equivalent of closing down eight coal-fired power stations.”

At under $2 each, there was never an incentive for manufacturers to move to higher-efficiency devices—in fact the increased cost was a positive disincentive. But somebody had to look at the larger picture, and the EPA did; now every power adaptor sold in the U.S.—and increasingly worldwide—is a high-efficiency, solid-state device. Nice work, people.

Now about that 52” flat-panel plasma TV you’ve been thinking about buying…

In the United States alone, those data centers accounted for 1.5 percent of the country’s electricity use in 2006 — more than the entire state of Massachusetts. And their power use could nearly double over five years, according to government reports.

Low-Power Design deliberately picked up the torch from Portable Design, which was all about energy efficient design. Looking at the macro-level implications—as evidenced by the data center example above—we realized that “green engineering” is all about creating energy-efficient designs. The power management techniques first developed for portable devices apply equally well to their plugged-in brethren. Now we won’t ignore you if your product doesn’t run off a battery. In fact you get bonus points if it uses less power than the state of Massachusetts (Rhode Island, even)!

Green engineering isn’t just good design, it can also save your customers a lot of green–as in money.

We cover the green angle in our news section in order to increase our readers’ awareness of the importance of the work they’re doing. But at heart we’re a design book, trying to provide the tools to help our readers get the job done. If you have a suggestion for how we can do a better job of it, please let us know.

“Electricity use from power-hungry gadgets is rising fast all over the world… Americans now have about 25 consumer electronic products in every household, compared with just three in 1980. Worldwide, consumer electronics now represent 15 percent of household power demand, and that is expected to triple over the next two decades. To satisfy the demand from gadgets will require building the equivalent of 560 coal-fired power plants, or 230 nuclear plants… Most energy experts see only one solution: mandatory efficiency rules specifying how much power devices may use.”

According to the Natural Resources Defense Council, gaming consoles alone–which kids like mine often leave on all the time so they can pick up where they left off–now use about the same amount of electricity each year as San Diego, the ninth-largest city in the country.

This is both reprehensible and indefensible. It’s also completely unnecessary. Low-power design, when scaled to hundreds of millions of devices, amounts to green engineering. Designing a more power-efficient wall wart or game console is not rocket science. First you have to wake up to the fact that it’s important to do so–then just do it.

Raising awareness of the social (“green”) implications of power-efficient design and providing the tools to help implement such products is the whole mission of Low-Power Design. The Times article makes it clear why going down this path is so important.

Note to CEA: Get Over It

Since the consumer electronics industry hasn’t seen the importance of energy-efficient design, government regulation is the obvious card to play. Since 1990, when the Energy Star standards for appliances went into effect, refrigerators are 45% more efficient on average and washing machines as much as 70%. Scaled to the national level this has precluded the need for hundreds of nuclear or coal-fired power plants.

Appliance Effiency Gains

In 1987 Congress gave the Energy Department the power to set efficiency standards for televisions, which aren’t covered by Energy Star. With the advent of large, flat-panel displays, televisions can now consume more energy than refrigerators, making them Tier 1 energy hogs. Still manufacturers–aggressively lead by the Consumer Electronics Association (CEA)–have fought every attempt to increase energy efficiency in consumer electronics (CE) products. According to Douglas Johnson, the senior director of technology policy at CEA, “Mandatory limits, such as we see in California, threaten to raise prices for consumers and reduce consumer choice.”

Baloney. If I have to pay $100 more for a flat-screen TV that draws half as much power, my total cost of ownership drops dramatically; the payback time depends on your utility rates, but with the average household watching five hours of TV daily, the payback will take place in a matter of months, after which my new TV is putting money in my pocket each month. That’s the sort of choice consumers want and the CEA is fighting to avoid. It’s time to get past “Just Say No!”

It’s also time to get on with the real work of low-power, energy-efficient “green” design. Over to you on that note.

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