December 2, 2010—Mentor Graphics has acquired most of the assets of CodeSourcery, the leading provider of open source GNU-based tool chains and services for advanced systems development. The acquisition builds on Mentor’s acquisition last year of Embedded Alley, whose runtime Linux and Android offerings moved Mentor firmly into the open-source embedded arena. The tools they’ll acquire from CodeSourcery should neatly leverage their investment in Embedded Alley and further solidify their position in the embedded space. Mark Mitchell, former CEO of CodeSourcery, will stay on as director of embedded tools for Mentor Graphics Embedded Software Division.

 With Mentor’s Nucleus RTOS powering over two billion mobile handsets, Mentor is hardly a Johnny Come Lately to the embedded market. Now in addition to their proprietary RTOS they can also offer Linux, Android and leading open-source tools for developing embedded systems. With Linux having a dominant share of the embedded market and Android a rapidly increasing presence in handsets, Mentor has positioned itself to ride these fast growing markets. The Sourcery G++ GNU-based IDE has a wide following in the open source community.

 Mentor isn’t the first software company with a proprietary RTOS to see the open source light. Wind River was doing very well with its VxWorks RTOS and initially spent time diss’ing Linux before deciding it made more sense to ride that horse than race against it. Today they have their own fork of Linux that integrates with their tools and databases, all of which opened up new markets for them and gave them some more credibility in the open source world. They acquired enough expertise in the process that Intel acquired them for it.

The OS business model nicely supplements the EDA industry’s standard charge-by-the-seat revenue model for tools, where you get paid once per year for a very finite number of seats. OTOH royalties on your RTOS that’s in a half billion handsets every year scales nicely. And you don’t have billions in fab costs to offset before you can make a profit.

EDA companies are all trying to find ways to grow faster than the slow pace of the EDA market. The Big Three each have different—if not that different—strategies. Synopsys continues to build a large portfolio of semiconductor IP that they guarantee will work together, easing the pain of IP integration and verification. Cadence’s EDA360 envisions an application-driven approach to system design, around which they’re reorganizing their tool offerings, not to mention their company. Mentor’s approach to faster growth is clearly to move more forcefully into the embedded space, adding a lot of open source tools to their toolkit. The extensive ecosystem and customer base that comes with Mentor’s two open-source acquisitions takes the edge off any risk.

U.C. Berkeley professor Jan Rabaey kicked off the 2010 International Symposium on Low-Power Electronics and Design (ISLPED) today in Austin with a challenge to programmers, hardware designers and their EDA tool providers: The deterministic Turing model has hit the power wall. If you want energy efficiency, forget accuracy. Consider statistical, even analog computing.

In his keynote talk—“Going Beyond Turing: Energy Efficiency in the Post-Moore Era”—Rabaey claimed that despite a decade of advances in energy efficiency—including dynamic and adaptive voltage scaling, architectural innovations and other clever power management techniques—“waste has been eliminated and we’re basically running out of options” at smaller geometries. In fact at 22 nm and below, energy savings won’t scale any more. Leakage is now the major problem, and scaling makes it worse. ISSCC 2011 will feature a general session panel that will brainstorm how to get the next major power reduction as you scale down.

It’s Hard to Determine

All computers today are built on a deterministic model; with the same inputs you get the same outputs every time. But what if you don’t need complete accuracy—if “being in the ballpark” is good enough? According to Rabaey, “If you’re willing to back away a bit from accuracy, you can gain quite a bit in efficiency.” You can get along with a lot less computing power if you’re willing to accept a range of outputs.

Why not in fact do the computation in analog? The outcome will be not a single number but a distribution. Analog is inherently accurate for simple computations, but improving accuracy is expensive in terms of energy efficiency, since in analog circuits there is an exponential relationship between the signal-to-noise ratio (SNR) and power. For up to a 30 dB SNR, analog does a good job; but to get better SNR, the power requirement goes up fast. There are a lot of applications that do well with a low SNR. While not exactly an application, the basically analog human brain works very well at a low SNR. Add a room full of screaming 7-year olds and its efficiency falls off a cliff.

Statistical computing doesn’t rely on probabilistic algorithms and it’s not the same as Boolean networks. Its inputs are deterministic or stochastic variables and its outputs are a range of numbers that follow a distribution curve. It relies on algorithms that display resilience in the presence of uncertainty (“noise”) and can still make reasonable estimates—with varying degrees of certainty—within parameters determined by the degree of uncertainty associated with the inputs.

ERSA and ANTs

Rabaey cited work done at Stanford on the Error Resistant System Architecture (ERSA), an attempt to define a hardware/software architecture that supports statistical computing. ERSA has resulted in significant power savings in dealing with streaming video, adding little detectable noise in the process. Rabaey also cited experiments on algorithmic noise tolerance (ANT) that resulted in a 2.5x energy saving for a barely detectable increase in error rate.

Rabaey pointed out that some applications are well suited to statistical computing techniques while others are not. Adding a bit of noise to streaming video is a reasonable tradeoff if it results in a major power saving. In contrast, medical, military and any mission-critical computing tasks need to remain deterministic. “Some errors roll off smoothly, while some are catastrophic.” And in any application, changes to the least significant bit (LSB) in a byte may be insignificant, while changes to the most significant bit (MSB) clearly are not.

Statistical computing may hold great promise, but designers and programmers need to change their thinking and EDA vendors need to deliver the tools. “We must start building statistics into all levels of the design process,” Rabaey concluded. “We have to break determinism. VHDL and Verilog are purely deterministic languages. We must spend time on error modeling of our hardware.” For this to happen, “The EDA community really needs to break out into the application space.”

Mentor, Synopsys, Cadence: the ball’s in your court, folks.

2009 EDA Market Share

Smith told Low-Power Design that the numbers reflect strictly tool sales and exclude business in peripheral markets in order to give the most accurate picture of EDA market share.

According to the report,

The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA.  This is an indication of the market shift caused by the move into the ESL Methodology.  Synopsys remains a strong number one.  We believe that the recent changes at Cadence have stopped their market share decline, similar to the changes made at Mentor, bringing in Wally Rhines during the switch to the RTL design methodology.

While I can hear the champagne corks popping in Wilsonville as far away as Austin, I’m sure that just as in the old Avis ads Mentor’s new motto will be “We’re #2, so we try harder!” With Cadence regaining traction, this will be a real horse race–and one from which all of us can only benefit.

Synopsys announced this morning that it had signed a definitive agreement to buy Virage Logic for $315M in what looks to be a mutually beneficial transaction. Synopsys needed to expand its semiconductor IP (SIP)  IP offerings, and Virage Logic—having built out their portfolio and positioned themselves as a “trusted IP vendor”—needed the additional financial muscle and marketing channels that Synopsys brings to the table.

Synopsis has long been building up an IP portfolio to supplement its EDA tool offerings and now has the largest such portfolio of any EDA firm. Fifteen years ago Synopsys started out with interface IP. Last year they acquired MIPS’ Analog Business Group (ABG), adding an analog portfolio.  Virage Logic, for its part, started out making SRAM instances and has expanded aggressively into other areas with their acquisitions of In-Chip Systems in 2002 (standard cell logic), Ingot Systems in 2007 (DDR memory controllers, PHYs, DLLs), Impinj in 2008 (their NVM technology) and ARC International  in 2009 (configurable processors). Last November Virage added a missing analog/mixed-signal capability with their acquisition of NXP’s horizontal advanced CMOS semiconductor IP (SIP) technology.

Synopsys CEO Aart de Geus said in this morning’s conference call, “Virage products provide a perfect complement to the Synopsys Interface analog IP portfolio by adding embedded memories, standard cells and programmable cores for control and multimedia subsystems.” All that and then some.

Acquiring Virage’s IP libraries complements Synopsys’ emphasis on electronic system-level (ESL) design. Synopsys’ recent acquisition of CoWare, whose software is focused on ESL, works hand in hand with expanding their IP offerings.  If you’re pushing system-level design, the more of the system you can provide the stronger your position. Synopsys, Mentor and Cadence are all taking different paths to the same place.

One possible glitch—won’t Virage’s ARC processor cores compete with those from ARM, long a close ally of Synopsys? Not according to either de Geus or John Koeter, Vice President of Marketing for Synopsys’ Solutions Group. Keoter: “The IP that we’re acquiring is really largely complementary to ARM. The ARC cores are really programmable cores, more for audio and video subsystems; they’re really ancillary processors to the ARM cores and not competitive with ARM on the CPU front.” Fair enough. ARC went toe to toe with ARM for years before retiring to those niches, albeit too late to survive.

Is IP a significant strategic growth initiative for Synopsys? According to Koeter, “Yes, it is. We view IP as a natural adjacency to the EDA market. It’s all about helping our customers get their complex chips out the door. As a corporate strategy we view IP as a growing adjacency to our core market. IP and systems represent about a $200M run rate for Synopsys, about 13% of the company. This is something that we’ve been investing in on both the IP and the systems side, and we view it as a nice growth opportunity.”

With EDA becoming a mature industry (read: flat or declining revenues off into the sunset), finding complementary revenue streams is key to survival; and doing so by acquisition during tough times is a fast track to growth. With the semiconductor IP (SIP) industry growing faster than either the semiconductor or EDA industries, this is an attractive area for expansion.

Expanding into IP from EDA makes sense for an equally basic reason: SoCs are becoming increasingly complex, requiring licensing IP from a variety of vendors. In the absence of totally uniform models—a core problem when it comes to analog IP—acquiring IP from a single vendor who can guarantee not only interoperability but compatibility throughout their tool chain is a compelling proposition.  And the more IP you can offer the more attractive your tool chain becomes.

Expect to see other EDA companies snap up SIP vendors over the next several months.

With $619 million in cash and equivalents at the end of Q1 and $401 million in current liabilities, Cadence can afford to make a cash offer, which is both prudent (the markets wouldn’t look kindly to their taking on more debt) and smart (don’t let this fish get away). Strategically it looks like a good move for Cadence and financially it’s certainly a win for Denali.

IP acquisitions are all the rage of late, with both semiconductor and EDA firms attempting to diversify out of mature (read: stagnant or shrinking) markets. Being made up mostly of bit players, the EDA industry is bound to consolidate more than it already has—that is if the larger semiconductor IP (SIP) vendors don’t get there first.

On the SIP side Virage Logic got tired of selling just SRAM instances and bought their way into standard cell logic, DDR memory controllers, PHYs and DLLS (Ingot); NVM IP (Impinj);  processors (ARC); and CMOS libraries, IP blocks and SoC infrastructure(NXP). Virage is out to become a one-stop IP shop for SoC designers, and they’re well on their way. Only Synopsys has a comparably broad IP lineup. ARM and MIPS have large IP ‘ecosystems’, which effectively passes IP costs and profits along to their partners, with whom they try not to compete.

MIPS Technologies tried to diversify into analog IP with their acquisition of Chipidea, which in retrospect might not have been such a bright idea. Not all acquisitions, while seeming to make sense at the time, are a match made in heaven. Hopefully Sandeep will get them back on track [Full disclosure: I used to work for MIPS.]

On the EDA side Synopsys recently bought CoWare, thereby buying their way back into the ESL market that they pioneered before losing interest (as did Cadence). In addition to a pretty complete tool flow, Synopsys also has a broad IP portfolio that they guarantee works together and with all their tools. This is an attractive argument among SoC designers who cringe at the thought of cobbling together ‘black box’ IP and models from a dozen different sources.

Mentor Graphics, who have consistently pursued ESL, still  holds the lead there. In the past 12 months alone Mentor has acquired embedded Linux and Android IP (Embedded Alley); BIST, ATPG and test pattern compression (LogicVision); automotive electrical and electronic systems IP (Freescale); and PCB design for manufacturing IP (Valor).  While placing a large marker in the embedded space, Mentor’s acquisitions seem primarily aimed at strengthening their current tool offerings.

Hampered by its former financial problems, Cadence is playing catch-up in the acquisitions game. The Denali ‘merger’ makes a lot of sense, adding the industry’s leading memory models and IP to Cadence’s product offerings. With only $43 million in annual revenues but a 30% operating margin, Denali was a prime acquisition target. My only question is why no one bought them sooner.

My prediction: The Denali party at DAC this year will be wilder than ever, with Sanjay leading the conga line. Sanjay: Where’s my ticket, dude?!

This evening Gary kicked off the 46th DAC with a pretty upbeat assessment, considering the the state of the economy. Long a believer in ESL–the need for it, if not the available tools–he sees RTL handover costing EDA vendors a lot of seats. However, as FPGAs continue to grow in popularity, EDA sales into that market will also grow.

ESL tools–promising and now starting to deliver smooth design flows from TLM to RTL to gate-level analysis–could make up for many if not most of those seats lost for traditional CAD tools. I’m not convinced the numbers add up, but the analysis makes sense.

The other thing vendors need to do, according to Smith, is to stop undercutting each other on price. At $350K per seat, it doesn’t take too many sales to sustain a healthy multi-billion dollar market. Growth won’t be explosive but it should continue to be healthy.

Referring again to the FPGA market, Gary wondered with all the consolidation that’s taken place of late in the EDA industry if it won’t wind up looking like the FPGA market, where lack of competition keeps prices and margins at a high level. Maybe the solution is one big happy oligopoly where everyone gets over this insane race to the bottom on price.

On that happy thought everyone checked their glasses (half full or half empty?) and looked around for the next friend. Gary will present detailed market prognostifications tomorrow morning at DAC’s formal launch.