USB has become the most successful PC peripheral interconnect ever defined, with over 10 billion USB 2.0 products installed today. Still, despite its convenience, USB has never been either the fastest or the lowest-power interconnect protocol out there. USB 3.0 seriously attempted to address both of those problems.
Facing competition from other high-speed interconnect protocols like 400- and 800-Mbps IEEE-1394 (FireWire) and HDMI—both of which targeted high-data rate streaming of video—in 2008 the USB Implementers Forum (USB-IF) formalized the specification for USB 3.0, which promises a “SuperSpeed” data rate of 5Gb/sec, a 10x improvement over USB 2.0 while at the same time reducing power consumption.
How can they do that you ask?
For starters, by eliminating polling. A USB 2.0 host continuously polls all peripheral devices to see if they have data to send to the host controller. All devices must therefore be on at all times, which not only wastes power but adds unnecessary traffic to the bus. In USB 3.0 polling is replaced by asynchronous notification. The host waits until an application tells it that there is a peripheral with data it needs to send to the host. The host then contacts that peripheral and requests that it send the data. When both are ready, the data is transferred.
USB 2.0 is inherently a broadcast protocol. USB 3.0 uses directed data transfer to and from the host and only the target peripheral. Only that peripheral turns on its transceiver, while others on the bus remain in powered-down mode. This results in less bus traffic and a considerably lower power profile.
SuperSpeed USB enables considerable power savings by enabling both upstream and downstream ports to initiate lower power states on the link. In addition multiple link power states are defined, enabling local power management control and therefore improved power usage efficiency. Eliminating polling and broadcasting also went a long way toward reducing power requirements. Finally, the increased speed and efficiency of USB 3.0 bus – combined with the ability to use data streaming for bulk transfers – further reduces the power profile of these devices. Typically the faster a data transfer completes, the faster system components can return to a low-power state. The USB-IF estimates the system power necessary to complete a 20 MB SuperSpeed data transfer will be 25% lower than is possible using USB 2.0.
The SuperSpeed specification brings over Link Power Management (LPM) from USB 2.0. LPM was first introduced in the Enhanced Host Controller Interface (EHCI) to accommodate high-speed PCI-based USB interfaces. Because of the difficulty of implementing it, LPM was slow to appear in USB 2.0 devices. It’s now required in USB 3.0 and for SuperSpeed devices supporting legacy high-speed peripherals. LPM is an adaptive power management model that uses link-state awareness to reduce power usage.
LPM defines a fast host transition from an enabled state to L1 Sleep (~10 µs) or L2 Suspend (after 3 ms of inactivity). Return from L1 sleep varies from ~70 µs to 1 ms; return from L2 Suspend mode is OS dependent. The fast transitions and close control of power at the link level enables LPM to manage power consumption in SuperSpeed systems with greater precision than was previously possible.
Link Power Management
Link power management enables a link to be placed into a lower power state when the link partners are idle. The longer a pair of link partners remain idle, the deeper the power savings that can be achieved by progressing from UO (link active) to Ul (link standby with fast exit), to U2 (link standby with slower exit), and finally to U3 (suspend). The table below summarizes the logical link states.
|Link State||Description||Key Characteristics||Device Clock||Exit Latency|
|U1||Link idle, fast exit||RX & TX quiesced||On or off||µs|
|U2||Link idle, slow exit||Clock gen circuit also quiesced||On or off||µs-ms|
|U3||Suspend||Portions of device power removed||Off||ms|
Most SuperSpeed devices, sensing inactivity on the link, will automatically reduce power to the PHY and transition from U0 to U1. Further inactivity will cause these devices to progressively lower power. The host or devices may then further idle the link (U2), or the host may even suspend it (U3).
Both devices and downstream ports can initiate Ul and U2 entry. Downstream ports have inactivity timers used to initiate Ul and U2 entry. Downstream port inactivity timeouts are programmed by system software. Devices may have additional information available that they can use to decide to initiate Ul or U2 entry more aggressively than inactivity timers. Devices can save significant power by initiating Ul or U2 more aggressively rather than waiting for downstream port inactivity timeouts.
Power Over USB
The USB Power Delivery (PD) Specification (2012) recognized the importance of delivering power over USB, increasing the maximum power to 10W at 5V, 36W at 12V, and 60W—now 100W—at 20V. Equipment with large power requirements such as laptops can now be powered over USB. Since power can now be delivered bidirectionally, this should do away with the ubiquitous power “bricks” and the countless proprietary connectors they require.
The USB PD Specification defines how USB Devices may negotiate for more current and/or higher or lower voltages over the USB cable (VBUS) than are defined in the USB2.0 and USB3.1 specifications. It allows devices with greater power requirements than can be met with today’s specification to get the power they require to operate from VBUS and negotiate with external power sources (e.g. wall warts). In addition, it allows a Source and Sink to swap roles such that a device could supply power to the Host. For example, a display could supply power to a notebook to charge its battery.
While the advantages of SuperSpeed USB are impressive, these devices are just beginning to appear in a world dominated by USB 2.0. For backward compatibility SuperSpeed devices must support both USB 2.0 and 3.0 link speeds, maintaining separate controllers and PHYs for full-speed, high-speed and SuperSpeed links. By maintaining a parallel system to support legacy devices, SuperSpeed’s designers accepted higher cost and complexity as a price worth paying to avoid compromising the speed advantage of their new architecture.