Low-Power Design White Papers

White Papers

Using Processors in the SOC Dataplane
Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of dataintensive functions that conventional control processors (CPUs) cannot handle. That’s why designers have, for a long time now, designed RTL blocks for these challenging functions. However, RTL blocks take a long time to design and verify. Plus they are not programmable and thus not flexible enough to easily handle multiple standards or post-tapeout design changes.

Optimize SOC Performance Using Memory Tuning and System Simulation
Memory tuning allows you to choose memory-related parameters for each on-chip processor core that balance system performance, processor area (cost), and memory size by exploring a target application’s sensitivity to these memory-system parameters. The processor core’s instruction-set simulator (ISS) plays a key and central role in this assessment because the ISS can model and report the expected system performance, providing a breakdown of memory-related stalls.

How to Minimize Energy Consumption While Maximizing ASIC and SOC Performance
Power has become a first-order concern for ASIC and SOC designers right next to performance and area, whether the design is for portable mobile devices, for networking boxes, or for any other application. Optimizing a design for energy at an application and system level has the potential to cut processor and local-memory energy requirements by as much as half in many cases through intelligent design trade-offs. The amount of power savings made at the early architectural level far outweighs any potential power savings that might be made later at the RTL or physical design levels.

How to Increase ASICs and SOC Computational Performance with Long-Word Processors
VLIW processors execute multiple independent instructions each clock cycle and provide a tremendous performance boost per clock cycle without incurring the exponential power-consumption increase caused by clock-rate increases. However, VLIW architectures have their own problems, particularly code bloat, which causes code footprints to balloon—thus increasing memory costs.

Get Your ASIC Off the Bus
This white paper provides short descriptions of the most common hardware mechanisms—buses, direct connections, and data queues—used to interconnect processor cores on ASICs and SOCs. Except where explicitly noted, this paper assumes a one-to-one correspondence between tasks and processors. In fact, multiple tasks can be mapped onto one time-sliced processor and some tasks can be implemented by other non-programmable hardware accelerator blocks.

Everything You Wanted to Know About SOC Memory (But Were Afraid to Ask)
This white paper discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. It discusses the essentials of SOC memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory. It covers the difference between 6T and 4T SRAM designs, the system design ramifications of NAND and NOR Flash ROM, and how DDR2 and DDR3 SDRAMS compare (the differences might surprise you).

Cut DSP Development Time – Get High Performance From C, No Assembly Required
Designers are asking their DSP cores to do more and more of the heavy workloads required for highly complex algorithms for filtering, FFT, MIMO, and other signal processing intensive applications. To get high performance from a conventional DSP core, developers have traditionally used assembly code programming, which is time consuming and difficult to maintain.

Low Power Design and Verification Techniques
There are many techniques that have been developed over the past decade to address the continuously aggressive power reduction requirements of most ASIC and SoC designs. They include clock gating, multi-switching (multi-Vt) threshold transistors, multi-supply multi voltage (MSMV), power gating with or without state retention, dynamic voltage and frequency scaling (DVFS), and substrate biasing. The use of any of these techniques comes at a cost and their benefit varies depending on the technique used.

Low-Power Physical Design with Olympus-SoC
Reducing power consumption has become a key design challenge at 45/32 nm technology nodes. For many designs, optimizing for power is as important as timing, due to the need to reduce package cost and extend battery life. However, the complexities of designing low-power chips can negatively impact performance and time to market. Designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners) that could have conflicting power, timing, signal integrity (SI), manufacturability, and area closure requirements.

Top Design Considerations for Low-Power Metering Applications
As green energy management becomes a global imperative, the idea of implementing intelligent systems and wireless technology to more efficiently use energy and other natural resources has become a pervasive reality. It began with a relatively simple idea. If you add embedded intelligence and a communications link to a traditional metering device, you have the ability to remotely access the data that the “smart meter” has collected.

How to Design Capacitive Touch & Proximity Sensing Technology into Your Application
What defines good human interface design, and how can system designers implement a smarter, friendlier and more intuitive solution? To begin answering these questions, it is helpful to view a human interface simply as a set of functional interactions with end users and their surroundings. These interactions can be subdivided into two logical groupings: inputs and outputs.

Simplifying Power Supply Design in FPGA-based Systems
FPGA-based systems have become common and are appropriate for many applications. However, by their nature, FPGAs are power-hungry devices with complex power delivery requirements and multiple voltage rails. When FPGA power consumption increases, performance requirements on sensitive analog and mixed signal subsystems also increase, particularly on clocking subsystems that provide low jitter timing references for the FPGA and other board-level components. By using clock sources with integrated power supply noise rejection, designers can simplify power supply design and mitigate these design challenges.

When to Use a Clock vs. an Oscillator
A wide range of timing solutions are available, including crystal oscillators (XO), voltage-controlled crystal oscillators (VCXO), and clocks. No one size fits all strategy applies when it comes to component selection. Picking the right device for a particular application is dependent on a number of factors, including whether or not the clocks must be synchronized to an externally provided reference clock, the system architecture of the processor and high speed serial data transmission ICs, and the frequency and jitter requirements of the end application.

Enhancing Power Delivery System Designs with CMOS-Based Isolated Gate Drivers
As emerging green standards challenge designers to deliver more energy-efficient, cost-effective and reliable power delivery systems in smaller form factors, the need for greater power and isolation device integration becomes increasingly important. A critical building block within ac-dc and isolated dc-dc power supplies is the isolated gate driver.

Low Power Design Basics
As the use of electronic devices pervades virtually every aspect of our lives, reducing power consumption must start at the semiconductor level. The power-saving techniques that are designed in at the chip level have a far-reaching impact. This is especially true with regard to the microcontrollers (MCUs) that serve as the intelligent engines behind a majority of today’s electronic devices.

Developing Reliable Isolation Circuits
Over the last four decades, optocouplers have been the “default” signal isolation device, but recent breakthroughs in silicon isolation technology have spawned smaller, faster, and more reliable and cost-effective solutions that have already begun supplanting optocouplers in many end applications. This white paper discusses industrial isolation issues and ways RF isolation technology can be applied to increase system robustness and performance.