Accellera Systems Initiative Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard
The new release of the Language Reference Manual extends compact modeling and behavior modeling of analog/mixed-signal (AMS) integrated circuits
San Francisco, Calif., June 3, 2014 (at the Design Automation Conference) — Accellera Systems Initiative (Accellera) announces it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs in which the effects of, and interactions among, different disciplines such as electrical, mechanical, fluid dynamics and thermal are important. The revised language reference manual is available for download from www.accellera.org.
Verilog-AMS is a mature standard originally released in 2000. It is built on top of the Verilog subset of the IEEE 1800-2012 "SystemVerilog—Unified Hardware Design, Specification and Verification Language.” IEEE 1800 was originally released in 2009 and supersedes the content of the IEEE 1364-2005 standard. The standard defines how analog behavior interacts with event-based functionality, providing a bridge between the analog and digital worlds. To model continuous-time behavior, Verilog-AMS is defined to be applicable to both electrical and non-electrical system descriptions. It supports conservative and signal-flow descriptions and can also be used to describe discrete (digital) systems and the resulting mixed-signal interactions.
The revised standard, Verilog-AMS 2.4, includes extensions to benefit verification, behavioral modeling and compact modeling. There are also several clarifications and over 20 errata fixes that improve the overall quality of the standard. Resources on how best to use the standard and a sample library with power and domain application examples are available.
“Verilog-AMS 2.4 is the result of the hard work and collaborative effort of the Verilog Analog/Mixed-Signal (AMS) Working Group (WG) who came together to deliver this standard,” said Scott Little, chair of the Verilog AMS WG. “This revision adds several features that users have been requesting for some time, such as supply sensitive connect modules, an analog event type to enable efficient electrical-to-real conversion and current checker modules."
The standard continues to be refined and extended to meet the expanding needs of various user communities. The Verilog-AMS WG is currently exploring options to align Verilog-AMS with SystemVerilog in the form of a dot standard to IEEE 1800. In addition, work is underway to focus on new features and enhancements requested by the community to improve mixed-signal design and verification.