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Product News

Industry’s lowest jitter PCIe clock buffers for communications, networking and data center systems  

TI clock buffers, combined with new WEBENCH tool, simplify clock tree design  

DALLAS (March 13, 2014) – Texas Instruments (TI) today introduced a pair of 4-output and 8-output high-speed current steering logic (HCSL) clock fanout buffers that support PCI Express (PCIe) Gen-1, Gen-2, Gen-3 interface standards. The LMK00334 creates four buffered copies of an input clock, while the LMK00338 produces eight buffered copies. They deliver 70 percent lower additive jitter and significantly higher supply noise rejection than competitive devices, providing system designers with ample jitter margin over the PCIe 3.0 specification. Both devices are supported in TI’s new WEBENCH Clock Architect to help simplify clock tree design for high-speed communications, networking, and data center systems, including servers, switches and routers.

For more information or to order samples and an evaluation module (EVM), visit www.ti.com/lmk00338-pr.

Key features and benefits of the LMK00334 and LMK00338:

  • Industry’s lowest additive jitter: 30 fs at 100 MHz (PCIe 3.0) and 86 fs at 12 KHz to 20 MHz (HCSL at 156.25 MHz) give designers more flexibility in timing budget allocation for the entire link.
  • Excellent noise rejection: High power supply rejection ratio (PSRR) of -75 dBc at100 MHz provides improved jitter performance and better noise immunity than competitive devices, enabling robust signal integrity.
  • Flexibility, universal inputs: Two universal inputs operate at up to 400 MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators.
  • Easy to use: Pin-mode control makes it easy for system designers to turn an individual output bank on and off.

The LMK00334 and LMK00338 can be combined with the CDCM9102 and the CDCM6208 PCIe clock generators to create a high-performance clock tree solution. TI’s clock distribution and fanout buffers give clock tree designers the flexibility, performance and advanced features they need to address a broad range of communications, networking, industrial and consumer applications.

Tools and support

Engineers can accelerate their clock tree designs with the LMK00334 and LMK00338, by using TI’s WEBENCH Clock Architect. It is the industry’s first timing design tool that can recommend and simulate a system clock tree solution from an exhaustive database of devices. It features phase-locked loop (PLL) filter design and the ability to simulate phase noise of the output clocks. The tool also provides the ability to simulate end-to-end jitter performance for the complete clock tree.

Both the LMK00334 and the LMK00338 utilize the LMK00338 evaluation module (EVM) to verify functionality and performance specifications. IBIS simulation models are also available for the LMK00334 and LMK00338.

Additional support is available on the Clocks & Timers Forum in the TI E2E Community, where engineers can search for solutions, get help, share knowledge and solve problems with fellow engineers and TI experts.

Availability, packaging and pricing

The LMK00334 is available today in a 5-mm by 5-mm, 32-pin WQFN package for a suggested retail price of US$1.20 in 1,000-unit quantities. The LMK00338 is available today in a 6-mm by 6-mm, 40-pin WQFN package for a suggested retail price of US$1.80 in 1,000-unit quantities.



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