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Cadence Announces Availability of Interconnect Workbench for Performance Analysis and Verification of ARM-Based SoCs  

SAN JOSE, CA--(Marketwired - October 29, 2013) - Cadence Design Systems, Inc. today announced the availability of Cadence Interconnect Workbench. A software solution providing cycle-accurate performance analysis of interconnects throughout the system-on-chip (SoC) design process, Interconnect Workbench quickly identifies design issues under critical traffic conditions and enables users to improve device performance and reduce time to market. Interconnect Workbench works in conjunction with Cadence Interconnect Validator for a complete functional verification and performance validation solution.

By automatically generating a performance testbench that incorporates Interconnect Validator and a complete suite of AMBA Verification IP, Interconnect Workbench reduces the time and effort commonly needed to create a test environment that previously required several weeks. To boost design performance, Interconnect Workbench allows users to compare potential architectures side by side on one screen.

"Ensuring that on-chip interconnects perform optimally is a baseline requirement for today's complex SoCs, system designers need the cycle-accurate analysis that Interconnect Workbench provides to make trade-offs and enhance their designs," said Andy Nightingale, director, System IP Products, Processor Division at ARM.

"Interconnect Workbench is specifically targeted at addressing the complexity of today's SoCs," said Ziv Binyamini, corporate vice president of System and Verification Solutions, System and Verification Group at Cadence. "In addition to optimizing performance of their ARM-based mobile, consumer, networking and storage SoCs, users can also get their designs to market much faster."

For more information on the Cadence Interconnect Workbench, visit www.cadence.com/news/iwb.

Cadence and ARM will also discuss the Interconnect Workbench in a technical session titled "Measure and Optimize System Performance of a Smartphone RTL Design" at ARM TechCon on October 30, 2013. For more details on the ARM TechCon session, visit http://schedule.armtechcon.com/session-id/48.




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