Xilinx Introduces UltraFast Design Methodology for Vivado Design Suite
Xilinx drives design methodology to enable accelerated and predictable design cycles
SAN JOSE, Calif., October 23, 2013 – Xilinx, Inc. today introduces the UltraFast design methodology for Vivado Design Suite, a comprehensive design methodology for enabling accelerated and predictable design cycles for design teams using the Vivado Design Suite. Xilinx is driving the methodology through its Vivado Design Suite, user guide, video and instructor led training and third party tools, and IP for ease of adoption and broad deployment.
Advanced algorithms used in today's communications, medical, defense, and consumer applications require devices and design tools that stretch the boundaries of complexity, performance, and power, while demanding ever faster and more predictable design cycles. In fact, just as in complex ASICs and SoCs, design productivity and associated schedules can vary from weeks to months for similar high end design projects. To address the root cause of the challenges, the UltraFast methodology was developed to cover all aspects of design, including board planning, design creation, IP integration, implementation, programming and hardware debug.
UltraFast Design Methodology for Vivado Design Suite
In order to help ease the adoption of the UltraFast design methodology, the Vivado Design Suite 2013.3 release provides methodology compliant design rule checks (DRC), guiding engineers throughout the design cycle. This release includes HDL and constraints templates enabling optimal quality of results. The UltraFast design methodology is also documented in a comprehensive user guide. Instructor and video led training are also available at www.xilinx.com/training.
To enable accelerated and predictable design cycles, Xilinx is also working with its Alliance Program ecosystem to integrate guidelines for the UltraFast methodology into ecosystem tools and IP.
"The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite to provide customers functional design analysis to verify UltraFast design methodology standards, properties and design rules," saidEllis Smith, CEO at Blue Pearl Software. "Our mutual customers have already seen how automation of the methodology helps reduce time spent writing accurate RTL code, lowers design risk, and improves quality of results."
Design teams can start using the UltraFast design methodology today. The first release of the UltraFast design methodology is targeted at Xilinx FPGAs and All Programmable 3D ICs. Future releases will include extensions for All Programmable SoCs. Learn more at www.xilinx.com/UltraFast.